公开(公告)号：US20240078735A1

公开(公告)日：2024-03-07

申请号：US18067837

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Xuefeng Tang ,  Vishwanath Shashikant Nikam ,  Nigel Poole ,  Kalyan Kumar Bhiravabhatla ,  Fei Xu ,  Zilin Ying

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.

公开(公告)号：US20170352182A1

公开(公告)日：2017-12-07

申请号：US15174110

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang ,  Xuefeng Tang ,  Jian Liang

IPC: G06T15/30 ,  G06T15/40 ,  G06T15/00

CPC classification number: G06T15/30 ,  G06T1/20 ,  G06T15/005 ,  G06T15/40 ,  G06T15/405

Abstract: A graphics processing unit (GPU) may perform a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene, including performing low-resolution z-culling of representations of the plurality of primitives based at least in part on a first set of culling z-values each having a first test size to determine a first set of visible primitives from the plurality of primitives. The GPU may further perform a rendering pass to render the plurality of tiles based at least in part on performing the low-resolution z-culling of representations of the first set of visible primitives based at least in part on a second set of culling z-values that represents a second test size to determine a second set of visible primitives from the first set of visible primitives, wherein the first test size is greater than the second test size.

公开(公告)号：US09824458B2

公开(公告)日：2017-11-21

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/60 ,  G06T1/20 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US10748239B1

公开(公告)日：2020-08-18

申请号：US16290761

申请日：2019-03-01

Applicant: QUALCOMM Incorporated

Inventor： Nigel Poole ,  Xuefeng Tang ,  Jian Liang

IPC: G06T1/20 ,  G06T1/60

Abstract: The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.

公开(公告)号：US20170084043A1

公开(公告)日：2017-03-23

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/20 ,  G06T15/80 ,  G06T1/60

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US20240221279A1

公开(公告)日：2024-07-04

申请号：US18609624

申请日：2024-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Dong Zhou

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a sliced low-resolution Z buffer (LRZ) that is communicatively coupled to each hardware slice of the plurality of hardware slices, and that comprises a plurality of LRZ regions. Each hardware slice is configured to store, in an LRZ region corresponding exclusively to the hardware slice among the plurality of LRZ regions, a pixel tile assigned to the hardware slice.

公开(公告)号：US11176734B1

公开(公告)日：2021-11-16

申请号：US17064188

申请日：2020-10-06

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu Alla ,  Adimulam Ramesh Babu ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah ,  Tao Wang ,  Xuefeng Tang ,  Thomas Edwin Frisinger ,  Andrew Evan Gruber

IPC: G06T15/40 ,  G06T15/00

Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.