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公开(公告)号：US11682109B2
公开(公告)日：2023-06-20
申请号：US17073218
申请日：2020-10-16
发明人： Kalyan Kumar Bhiravabhatla , Krishnaiah Gummidipudi , Ankit Kumar Singh , Andrew Evan Gruber , Pavan Kumar Akkaraju , Srihari Babu Alla , Jonnala Gadda Nagendra Kumar , Vishwanath Shashikant Nikam
摘要： This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.
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公开(公告)号：US12079897B2
公开(公告)日：2024-09-03
申请号：US17935031
申请日：2022-09-23
发明人： Kalyan Kumar Bhiravabhatla , Andrew Evan Gruber , Rahul Sunil Kukreja , Vishwanath Shashikant Nikam , Tao Wang , Jian Liang
CPC分类号： G06T1/20 , G06T1/60 , G06T15/005 , G06T15/405
摘要： This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US12002142B2
公开(公告)日：2024-06-04
申请号：US17373718
申请日：2021-07-12
发明人： Tushar Garg , Thomas Edwin Frisinger , Nigel Poole , Vishwanath Shashikant Nikam , Vijay Kumar Donthireddy
CPC分类号： G06T15/005 , G06F11/3485 , G06T1/20
摘要： The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.
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公开(公告)号：US20240078735A1
公开(公告)日：2024-03-07
申请号：US18067837
申请日：2022-12-19
发明人： Jian Liang , Andrew Evan Gruber , Tao Wang , Xuefeng Tang , Vishwanath Shashikant Nikam , Nigel Poole , Kalyan Kumar Bhiravabhatla , Fei Xu , Zilin Ying
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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公开(公告)号：US11908079B2
公开(公告)日：2024-02-20
申请号：US17658634
申请日：2022-04-08
发明人： Renju Boben , Kalyan Kumar Bhiravabhatla , Vishwanath Shashikant Nikam , Suvam Chatterjee , Ankit Kumar Singh , Abhishek Lal , Sampathkumar Periasamy
CPC分类号： G06T17/20 , G06T15/005
摘要： This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.
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公开(公告)号：US11615504B2
公开(公告)日：2023-03-28
申请号：US17229697
申请日：2021-04-13
发明人： Vishwanath Shashikant Nikam , Kalyan Kumar Bhiravabhatla , Suvam Chatterjee , Siva Satyanarayana Kola , Abhishek Lal , Andrew Evan Gruber
摘要： The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.
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公开(公告)号：US11037358B1
公开(公告)日：2021-06-15
申请号：US16733919
申请日：2020-01-03
IPC分类号： G06T15/00
摘要： The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine at least some shading data for each of a plurality of patches. Further, aspects of the present disclosure can store the at least some shading data for each of the plurality of patches in a GMEM. Additionally, aspects of the present disclosure can communicate the at least some shading data for each of the plurality of patches. In some aspects, the present disclosure can configure the GMEM for storing the at least some shading data for each of a plurality of patches. Aspects of the present disclosure can also calculate when the GMEM has stored a maximum amount of shading data. Moreover, aspects of the present disclosure can divide each of the plurality of patches into one or more sub-patches when the GMEM has stored the maximum amount of shading data.
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