公开(公告)号：US20250104325A1

公开(公告)日：2025-03-27

申请号：US18476258

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Vishwanath Shashikant Nikam ,  Kalyan Kumar Bhiravabhatla ,  Sampathkumar Periasamy ,  Suvam Chatterjee

IPC: G06T15/00 ,  G06T15/04

Abstract: Efficiently handling restart indices during tile-based deferred rendering (TBDR) by graphics processing units (GPUs) is disclosed herein. In some aspects, a processor circuit of a GPU determines, during a tile sorting pass, a location of a restart index in a plurality of indices of an index buffer associated with a primitive topology, and determines a skip count indicating a number of indices to skip during a tile rendering pass, based on the primitive topology and the location of the restart index. In some aspects, the processor circuit also determines visibility statuses corresponding to primitives of the primitive topology, and generates visibility data comprising the visibility statuses and the skip count. Subsequently, during the tile rendering pass, the processor circuit bypasses fetching of the restart index, based on the skip count. According to some aspects, the processor circuit may also assemble the primitives based on the visibility data.

公开(公告)号：US11908079B2

公开(公告)日：2024-02-20

申请号：US17658634

申请日：2022-04-08

Applicant: QUALCOMM Incorporated

Inventor： Renju Boben ,  Kalyan Kumar Bhiravabhatla ,  Vishwanath Shashikant Nikam ,  Suvam Chatterjee ,  Ankit Kumar Singh ,  Abhishek Lal ,  Sampathkumar Periasamy

IPC: G06T17/20 ,  G06T15/00

CPC classification number: G06T17/20 ,  G06T15/005

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

公开(公告)号：US11615504B2

公开(公告)日：2023-03-28

申请号：US17229697

申请日：2021-04-13

Applicant: QUALCOMM Incorporated

Inventor： Vishwanath Shashikant Nikam ,  Kalyan Kumar Bhiravabhatla ,  Suvam Chatterjee ,  Siva Satyanarayana Kola ,  Abhishek Lal ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.