公开(公告)号：US10521321B2

公开(公告)日：2019-12-31

申请号：US15850967

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Alex Kwang Ho Jong ,  Jay Chunsup Yun ,  Donghyun Kim ,  Rahul Gulati ,  Brendon Lewis Johnson ,  Andrew Evan Gruber

IPC: G06F11/00 ,  G06F11/277 ,  G06T1/20 ,  G06T7/00 ,  G06F11/22

Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.

公开(公告)号：US10481202B2

公开(公告)日：2019-11-19

申请号：US15835227

申请日：2017-12-07

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Nishi Bhushan Singh ,  Rahul Gulati ,  Pranjal Bhuyan ,  Rakesh Kumar Kinger ,  Roberto Averbuj

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/319 ,  G01R31/3183 ,  G01R31/3185 ,  G06F9/448

Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.

公开(公告)号：US10467723B2

公开(公告)日：2019-11-05

申请号：US15850907

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Brendon Lewis Johnson ,  Andrew Evan Gruber ,  Jay Chunsup Yun ,  Rahul Gulati ,  Donghyun Kim ,  Alex Kwang Ho Jong

IPC: G09G5/00 ,  G06T1/20 ,  G06T1/60 ,  G06F11/10 ,  G06T7/00 ,  G09G5/36 ,  B60R1/00 ,  B60K35/00

Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.

公开(公告)号：US10389379B2

公开(公告)日：2019-08-20

申请号：US15594322

申请日：2017-05-12

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Palkesh Jain ,  Pranjal Bhuyan ,  Mohammad Reza Kakoee

IPC: H03M13/01 ,  H03M13/00 ,  G06F11/22

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

公开(公告)号：US20190181982A1

公开(公告)日：2019-06-13

申请号：US16216220

申请日：2018-12-11

Applicant: QUALCOMM Incorporated

Inventor： Robert Hardacker ,  Rahul Gulati ,  Alex Jong

IPC: H04L1/00 ,  G07C5/08 ,  H03M13/09 ,  H04L12/40

Abstract: Systems and method for error detection in automobile tell-tales are provided. An initial cyclic redundancy check (CRC) for a tell-tale to be calculated and stored at a primary control system within the vehicle. When a fault or condition is detected which generates the tell-tale, the primary control system passes video information to a display embedded control unit (ECU) along with the initial CRC. A circuit in the display ECU performs its own CRC calculation and compares the initial CRC to the calculated CRC. If there is not a match, then a fault indication may be provided to the primary control system for action by the primary control system. Still further, back up or fail-operational options may be invoked so that the tell-tale is provided to the operator.

公开(公告)号：US20190132555A1

公开(公告)日：2019-05-02

申请号：US16125231

申请日：2018-09-07

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Hao Chu ,  Rahul Gulati ,  Robert Hardacker ,  Alex Jong ,  Mohammad Reza Kakoee ,  Behnam Katibian ,  Anshuman Saxena ,  Sanjay Vishin ,  Sanat Kapoor

IPC: H04N7/18 ,  B60R1/00

Abstract: Methods and systems to broadcast sensor outputs in an automotive environment allow sensors such as cameras to output relatively unprocessed (raw) data to two or more different processing circuits where the processing circuits are located in separate and distinct embedded control units (ECUs). A first one of the two or more different processing circuits processes the raw data for human consumption. A second one of the two or more different processing circuits processes the raw data for machine utilization such as for autonomous driving functions. Such an arrangement allows for greater flexibility in utilization of the data from the sensors without imposing undue latency in the processing stream and without compromising key performance indices for human use and machine use.

公开(公告)号：US09897651B2

公开(公告)日：2018-02-20

申请号：US15059341

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Virendra Bansal ,  Rahul Gulati ,  Palkesh Jain ,  Roberto Avanzi

IPC: G01R31/317 ,  G06F1/04 ,  H03K3/037 ,  H03K5/14 ,  G01R31/319 ,  H03K5/00

CPC classification number: G01R31/31727 ,  G01R31/31922 ,  G06F1/04 ,  H03K3/037 ,  H03K5/14 ,  H03K2005/00058

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.

公开(公告)号：US20170357557A1

公开(公告)日：2017-12-14

申请号：US15176745

申请日：2016-06-08

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Virendra Bansal ,  Rahul Gulati

IPC: G06F11/16

CPC classification number: G06F11/1608 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/184 ,  G06F11/187 ,  G06F2201/805 ,  G06F2201/82

Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

公开(公告)号：US20170255223A1

公开(公告)日：2017-09-07

申请号：US15059341

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Virendra Bansal ,  Rahul Gulati ,  Palkesh Jain ,  Roberto Avanzi

IPC: G06F1/04 ,  H03K5/14 ,  H03K3/037

CPC classification number: G01R31/31727 ,  G01R31/31922 ,  G06F1/04 ,  H03K3/037 ,  H03K5/14 ,  H03K2005/00058

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.

公开(公告)号：US11424621B2

公开(公告)日：2022-08-23

申请号：US16774023

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Rahul Gulati

IPC: H02J4/00 ,  G06F1/18 ,  G06F1/3203 ,  H01L23/525 ,  H01L27/08 ,  H02J9/00

Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.