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    Devices, systems and methods using through silicon optical interconnects
    16.
    发明授权
    Devices, systems and methods using through silicon optical interconnects 有权
    使用硅光学互连的器件，系统和方法

    公开(公告)号：US09478528B2

    公开(公告)日：2016-10-25

    申请号：US13771638

    申请日：2013-02-20

    Applicant: Qualcomm Incorporated

    Inventor： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew M. Nowak

    IPC: H01L25/16 ,  H01L25/00 ,  H04B10/80 ,  H01L23/00

    CPC classification number: H01L25/167 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H04B10/803 ,  H01L2924/00012

    Abstract: Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die.

    Abstract translation: 一些实施方案提供包括第一管芯和光学接收器的半导体器件。 第一模具包括具有足够薄的厚度以允许光信号穿过背侧层的背面层。 光接收器被配置为通过第一管芯的背侧层接收多个光信号。 在一些实现中，每个光信号源自耦合到第二管芯的对应的光发射器。 在一些实施方式中，背面层是模具基板。 在一些实现中，光信号穿过背侧层的衬底部分。 第一裸片还包括有源层。 光接收器是有源层的一部分。 在一些实施方案中，半导体器件包括包括光发射器的第二裸片。 第二模具耦合到第一模具的背面。

    DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE
    19.
    发明申请
    DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE 有权
    用于测试半导体连续性的DAISY链接连接

    公开(公告)号：US20140264331A1

    公开(公告)日：2014-09-18

    申请号：US13800976

    申请日：2013-03-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M. Nowak ,  Glen T. Kim ,  Mark C. Chan ,  Shiqun Gu

    IPC: H01L21/66

    CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

    Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。

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