公开(公告)号：US20160349320A1

公开(公告)日：2016-12-01

申请号：US14794774

申请日：2015-07-08

Applicant: QUALCOMM Incorporated

Inventor： Michael Laisne ,  Bruce Cochrane ,  Fnu Praveen Ipe

IPC: G01R31/3177 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/318508 ,  G01R31/318536 ,  G06F11/2236

Abstract: A wrapper for automatic test pattern generation uses the functional bus when testing cores on an integrated circuit device. The functional bus is between the bus wrapper and the cores. During normal operation, the functional bus operates as a standard bus to communicate functional inputs and outputs between the cores and in/out of the integrated circuit device. During test operation, test signals are communicated on the functional bus. As a result, each core does not require its own wrapper; this allows the bus wrapper to reduce the area occupied by test circuitry.

Abstract translation: 在集成电路设备上测试核心时，自动测试模式生成的包装器使用功能总线。 功能总线位于总线封装和内核之间。 在正常操作期间，功能总线作为标准总线进行工作，以在芯体和集成电路器件的输出之间传递功能输入和输出。 在测试操作期间，在功能总线上通信测试信号。 因此，每个核心都不需要自己的包装器; 这使得总线封装可以减少测试电路占用的面积。

公开(公告)号：US20140264331A1

公开(公告)日：2014-09-18

申请号：US13800976

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M. Nowak ,  Glen T. Kim ,  Mark C. Chan ,  Shiqun Gu

IPC: H01L21/66

CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。

公开(公告)号：US20170010325A1

公开(公告)日：2017-01-12

申请号：US14794635

申请日：2015-07-08

Applicant: QUALCOMM Incorporated

Inventor： Arul Subbarayan ,  Sachin Badole ,  Archana Matta ,  Madhura Hegde ,  Sergio Mier ,  Shankarnarayan Bhat ,  Michael Laisne ,  Glenn Mark Plowman ,  Prakash Krishnan

IPC: G01R31/317

CPC classification number: G01R31/31707 ,  G01R31/31718 ,  G01R31/31835 ,  G01R31/318371

Abstract: A method and apparatus for adaptive test time reduction is provided. The method begins with running a predetermined number of structural tests on wafers or electronic chips. Pass/fail data is collected once the predetermined number of structural tests have been run. This pass/fail data is then used to determine which of the predetermined number of structural tests are consistently passed. The consistently passed tests are then grouped into slices within the test vectors. Once the grouping has been performed, the consistently passed tests are skipped when testing future production lots of the wafers or electronic chips. A sampling rate may be modulated if it is determined that adjustments in the tests performed are needed. In addition, a complement of the tests performed on the wafers may be performed on the electronic chips to ensure complete test coverage.

Abstract translation: 提供了一种用于自适应测试时间缩短的方法和装置。 该方法开始于在晶片或电子芯片上运行预定数量的结构测试。 一旦运行了预定数量的结构测试，就会收集通过/失败数据。 然后，该通过/失败数据用于确定一致地通过预定数量的结构测试中的哪一个。 然后将一致的通过的测试分组到测试向量中的切片中。 一旦分组完成，在测试未来大量晶圆或电子芯片的时候，会一直跳过测试。 如果确定需要进行测试的调整，则可以调制采样率。 此外，可以在电子芯片上执行对晶片执行的测试的补充，以确保完整的测试覆盖。

公开(公告)号：US09024315B2

公开(公告)日：2015-05-05

申请号：US13800976

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M Nowak ,  Glen T Kim ,  Mark C Chan ,  Shiqun Gu

IPC: H01L23/58 ,  H01L21/66

CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。