公开(公告)号：US20170125575A1

公开(公告)日：2017-05-04

申请号：US15403381

申请日：2017-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  MASAO UCHIDA ,  NOBUYUKI HORIKAWA ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L27/06

CPC classification number: H01L29/7803 ,  H01L21/28 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/80

Abstract: In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

公开(公告)号：US20160315203A1

公开(公告)日：2016-10-27

申请号：US15089542

申请日：2016-04-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKAYUKI WAKAYAMA

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6606

Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to direction of crystal orientations of the semiconductor substrate.

Abstract translation: 根据本公开的一个方面的半导体器件包括具有第一导电类型并具有主表面和背表面的半导体衬底，具有第一导电类型并设置在主表面上的碳化硅半导体层，具有 第二导电类型并且设置在碳化硅半导体层内，具有第二导电类型并且设置在碳化硅半导体层内的边缘终端区域，包围阻挡区域的边缘终端区域，设置在碳化硅半导体层上的第一电极 以及设置在所述背面上的第二电极，其中，所述阻挡区域中的每一个与所述碳化硅半导体层具有多边形边界，并且所述多边形边界的每一侧相对于所述多边形边界的角度为0°至5° -20>半导体衬底的晶体取向方向。

公开(公告)号：US20160308072A1

公开(公告)日：2016-10-20

申请号：US15089383

申请日：2016-04-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKAYUKI WAKAYAMA ,  MASASHI HAYASHI ,  TATSUYA KUNISATO

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6606

Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, a guard ring region having a second conductivity type and disposed within the silicon carbide semiconductor layer, a floating region having the second conductivity type and disposed within the silicon carbide semiconductor layer, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate, wherein the guard ring region and the floating region each include a pair of a high-concentration region having the second conductivity type and a low-concentration region having the second conductivity type.

Abstract translation: 根据本公开的一个方面的半导体器件包括具有第一导电类型并具有主表面和背表面的半导体衬底，具有第一导电类型的碳化硅半导体层并且设置在半导体衬底的主表面上 具有第二导电类型并且设置在碳化硅半导体层内的保护环区域，具有第二导电类型的浮动区域并且设置在碳化硅半导体层内，设置在碳化硅半导体层上的第一电极和第二电极 设置在半导体衬底的背面上的电极，其中保护环区域和浮置区域各自包括一对具有第二导电类型的高浓度区域和具有第二导电类型的低浓度区域。

公开(公告)号：US20150357405A1

公开(公告)日：2015-12-10

申请号：US14726635

申请日：2015-06-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： YUKI UEDA ,  MASAO UCHIDA

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device comprises a semiconductor substrate, a silicon carbide semiconductor layer of a first conductivity type on the semiconductor substrate, at least one ring-shaped region of a second conductivity type in the silicon carbide semiconductor layer, a first insulating film in contact with a part of the silicon carbide semiconductor layer, and a second insulating film which has a relative dielectric constant larger than a relative dielectric constant of the first insulating film and which is in contact with a part of the at least one ring-shaped region. In the semiconductor device, the at least one ring-shaped region is located in a termination region. The termination region surrounds a semiconductor element region when viewed from the direction perpendicular to a principal surface of the semiconductor substrate.

Abstract translation: 半导体器件包括半导体衬底，半导体衬底上的第一导电类型的碳化硅半导体层，碳化硅半导体层中的至少一个第二导电类型的环形区域，与 以及第二绝缘膜，所述第二绝缘膜的相对介电常数大于所述第一绝缘膜的相对介电常数并且与所述至少一个环形区域的一部分接触。 在半导体器件中，至少一个环形区域位于终端区域中。 当从垂直于半导体衬底的主表面的方向观察时，端接区域围绕半导体元件区域。