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    Flash memory cell with dual erase modes for increased cell endurance
    11.
    发明授权
    Flash memory cell with dual erase modes for increased cell endurance 有权

    公开(公告)号：US10482975B2

    公开(公告)日：2019-11-19

    申请号：US16008234

    申请日：2018-06-14

    Applicant: Microchip Technology Incorporated

    Inventor： Luc Reboulet ,  James Walls

    IPC: G11C16/16 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

    Abstract: An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

    Flash Memory Cell with Dual Erase Modes for Increased Cell Endurance
    12.
    发明申请
    Flash Memory Cell with Dual Erase Modes for Increased Cell Endurance 审中-公开

    公开(公告)号：US20190287624A1

    公开(公告)日：2019-09-19

    申请号：US16008234

    申请日：2018-06-14

    Applicant: Microchip Technology Incorporated

    Inventor： Luc Reboulet ,  James Walls

    IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34

    Abstract: An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

    Memory Cell With Oxide Cap And Spacer Layer For Protecting A Floating Gate From A Source Implant
    13.
    发明申请
    Memory Cell With Oxide Cap And Spacer Layer For Protecting A Floating Gate From A Source Implant 审中-公开

    公开(公告)号：US20190097027A1

    公开(公告)日：2019-03-28

    申请号：US16110330

    申请日：2018-08-23

    Applicant: Microchip Technology Incorporated

    Inventor： Mel Hymas ,  Bomy Chen ,  Greg Stom ,  James Walls

    IPC: H01L29/66 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/265

    Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

    Resistive memory cell having a reduced conductive path area
    15.
    发明授权
    Resistive memory cell having a reduced conductive path area 有权
    具有减小的导电路径面积的电阻式存储单元

    公开(公告)号：US09318702B2

    公开(公告)日：2016-04-19

    申请号：US14184268

    申请日：2014-02-19

    Applicant: Microchip Technology Incorporated

    Inventor： Paul Fest ,  James Walls

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

    Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.

    Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM）的方法可以包括形成底部电极层，氧化底部电极层的暴露区域以形成氧化物区域，去除接近氧化物的底部电极层的区域 从而形成具有与氧化物区域相邻的尖端区域的底部电极，并且在底部电极和氧化物区域的至少一部分上形成电解质区域和顶部电极，使得电解质区域配置在尖端区域 并且当将电压偏压施加到存储单元时，提供从底电极的尖尖区域到顶电极的导电细丝或空位链形成的路径。 还公开了通过这种方法形成的存储单元和存储单元阵列。

    Floating gate spacer for controlling a source region formation in a memory cell
    16.
    发明授权
    Floating gate spacer for controlling a source region formation in a memory cell 有权

    公开(公告)号：US10424589B2

    公开(公告)日：2019-09-24

    申请号：US15983461

    申请日：2018-05-18

    Applicant: Microchip Technology Incorporated

    Inventor： James Walls ,  Mel Hymas ,  Sajid Kabeer

    IPC: H01L21/225 ,  H01L21/266 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/66 ,  H01L29/788

    Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

    Resistive Memory Cell With Sloped Bottom Electrode
    19.
    发明申请
    Resistive Memory Cell With Sloped Bottom Electrode 审中-公开

    公开(公告)号：US20180287057A1

    公开(公告)日：2018-10-04

    申请号：US16001332

    申请日：2018-06-06

    Applicant: Microchip Technology Incorporated

    Inventor： James Walls ,  Paul Fest

    IPC: H01L45/00

    Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

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