公开(公告)号：US20230282604A1

公开(公告)日：2023-09-07

申请号：US18106499

申请日：2023-02-07

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Isabella Song ,  Wen-Chin Tsai

IPC: H01L23/00 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/16 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/3135 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/14361 ,  H01L2924/1431 ,  H01L2224/13644 ,  H01L2224/13082 ,  H01L2224/13575 ,  H01L2224/13005 ,  H01L2224/1357 ,  H01L2924/1011

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.

公开(公告)号：US11227846B2

公开(公告)日：2022-01-18

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US10739206B2

公开(公告)日：2020-08-11

申请号：US15859518

申请日：2017-12-30

Applicant: MediaTek Inc.

Inventor： Chi-Wen Pan ,  Pei-Yu Huang ,  Sheng-Liang Kuo ,  Jih-Ming Hsu ,  Tai-Yu Chen ,  Yun-Ching Li ,  Wei-Ting Wang

IPC: G01K1/00 ,  G01K7/00 ,  G01K1/20 ,  G06F1/20 ,  G01K7/42 ,  G01K7/16 ,  G01K13/00

Abstract: The surface temperature of a portable device is estimated. A sensor detects the internal temperature of the portable device. The internal temperature and an ambient temperature are used as input to a circuit model that describes thermal behaviors of the portable device. Dynamic thermal management may be performed based on the estimated surface temperature.

公开(公告)号：US20200243462A1

公开(公告)日：2020-07-30

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US09632841B2

公开(公告)日：2017-04-25

申请号：US14290933

申请日：2014-05-29

Applicant: MEDIATEK INC.

Inventor： Chi-Wei Yang ,  Che-Ming Hsu ,  Wen-Tsan Hsieh ,  Tai-Yu Chen ,  Jih-Ming Hsu ,  Ming-Hsien Lee

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/50

CPC classification number: G06F9/5094 ,  Y02D10/22

Abstract: An electronic device has a processing system and a management circuit. The processing system executes an application. The management circuit detects an operating behavior of the application during execution of the application, analyzes the detected operating behavior of the application to generate an application identification result, and configures an application-dependent task according to at least the application identification result.

公开(公告)号：US20160148854A1

公开(公告)日：2016-05-26

申请号：US14925982

申请日：2015-10-29

Applicant: Mediatek Inc.

Inventor： Wen-Sung Hsu ,  Tai-Yu Chen

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/34 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/014

Abstract: A packaging substrate includes a core layer having a first surface and a second surface. A group of ground pads is disposed on the second surface within a central region. A group of first power pads is disposed on the second surface within the central region. A plurality of signal pads is disposed on the second surface within a peripheral region that encircles the central region on the second surface. A first block-type via is embedded in the core layer within the central region. The group of ground pads is electrically connected to the first block-type via. A second block-type via is embedded in the core layer within the central region. The group of first power pads is electrically connected to the second block-type via.

Abstract translation: 包装衬底包括具有第一表面和第二表面的芯层。 一组接地焊盘设置在中心区域内的第二表面上。 一组第一电源焊盘设置在中心区域内的第二表面上。 多个信号焊盘设置在围绕第二表面的中心区域的周边区域内的第二表面上。 第一块型通孔嵌入在中心区域内的芯层中。 接地焊盘组电连接到第一块型通孔。 第二块型通孔嵌入在中心区域内的芯层中。 第一电源焊盘组电连接到第二块型通孔。

公开(公告)号：US20150346785A1

公开(公告)日：2015-12-03

申请号：US14294170

申请日：2014-06-03

Applicant: Mediatek Inc.

Inventor： Tai-Yu Chen ,  Wen-Tsan Hsieh ,  Chi-Wei Yang

IPC: G06F1/20 ,  H04M1/18

CPC classification number: G06F1/206 ,  H04M1/18

Abstract: The present invention provides a thermal control method and a thermal control system. The thermal control method comprises: detecting a temperature variance of a component of the electronic device to generate a detecting result; and determining a temperature threshold value for the integrated circuit as a throttling point according to the detecting result. The thermal control system comprises: a detecting unit, for detecting a temperature variance of a component of the electronic device to generate a detecting result; and a determining unit, for determining a temperature threshold value for the integrated circuit as a throttling point according to the detecting result.

Abstract translation: 本发明提供一种热控制方法和热控制系统。 热控制方法包括：检测电子设备的部件的温度变化以产生检测结果; 以及根据检测结果确定集成电路的温度阈值作为节流点。 热控制系统包括：检测单元，用于检测电子设备的部件的温度变化以产生检测结果; 以及确定单元，用于根据检测结果将集成电路的温度阈值确定为节流点。

公开(公告)号：US12021068B2

公开(公告)日：2024-06-25

申请号：US17492693

申请日：2021-10-04

Applicant: MEDIATEK INC.

Inventor： Bo-Jiun Yang ,  Wen-Sung Hsu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Kun-Ting Hung

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.

公开(公告)号：US20220102297A1

公开(公告)日：2022-03-31

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200243464A1

公开(公告)日：2020-07-30

申请号：US16802576

申请日：2020-02-27

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01Q1/02 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/373

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.