公开(公告)号：US06921937B2

公开(公告)日：2005-07-26

申请号：US10378573

申请日：2003-03-03

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L23/58

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/792 ,  Y10T29/41

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract translation: 本发明提供一种闪速存储器集成电路及其制造方法。 在可擦除可编程只读存储器（EPROM）器件中的隧道电介质被含氢化合物，特别是氨氮化。 因此，氢与氮一起并入隧道电介质中。 蚀刻并完成了栅极堆叠，包括保护性侧壁间隔物和电介质盖，并且叠置有对羟基和氢物质的屏障。 尽管衬垫有利地将杂质扩散减少到隧道电介质和衬底界面，但是在任何随后的氢退火中也可以减少氢扩散。 然而，在先前暴露于氨中时，向隧道电介质提供氢。

公开(公告)号：US06791138B2

公开(公告)日：2004-09-14

申请号：US10277923

申请日：2002-10-23

Applicant: Ronald A. Weimer ,  Er-Xuan Ping

Inventor： Ronald A. Weimer ,  Er-Xuan Ping

IPC: H01L27108

CPC classification number: H01L21/823475 ,  H01L21/3145 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L23/3192 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.

Abstract translation: 公开了一种在玻璃膜和存储器件的有源区之间形成的复合阻挡层。 复合阻挡层包括通过原子沉积工艺形成的氧化物层和形成在氧化物层上的绝缘层，例如氮化物阻挡层。 复合阻挡层消除了杂质原子从玻璃膜扩散到器件的有源区中。

公开(公告)号：US06596595B1

公开(公告)日：2003-07-22

申请号：US09620442

申请日：2000-07-20

Applicant: Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

Inventor： Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

IPC: H01L21336

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/2807 ,  H01L21/32105

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract translation: 用于半导体器件的导电结构包括多层结构。 第一层包括含硅的材料，例如多晶硅和锗锗。 在第一层上形成阻挡层，阻挡层包括金属硅化物或金属硅化物氮化物。 在阻挡层上形成顶部导电层。 顶部导电层可以包括金属或金属硅化物。 可以进行选择性氧化以减少包含多层结构的结构中所选材料的氧化量，例如多层导电结构。 选择性氧化在单晶片快速热处理系统中进行，其中使用包括氢的所选择的环境来确保所选择的材料如钨或金属氮化物的低氧化。

公开(公告)号：US06462371B1

公开(公告)日：2002-10-08

申请号：US09229320

申请日：1999-01-13

Applicant: Ronald A. Weimer ,  John T. Moore

Inventor： Ronald A. Weimer ,  John T. Moore

IPC: H01L27108

CPC classification number: H01L21/0276 ,  H01L21/02126 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3145 ,  H01L21/3146 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S257/90 ,  Y10S438/97

Abstract: The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

Abstract translation: 本发明涉及掺杂有碳的硅和氧的膜以及集成电路技术中的膜的使用，例如电容器结构，DRAM构造，半导体材料组件，蚀刻工艺以及用于形成电容器，DRAM和半导体的方法 材料组件

公开(公告)号：US06177127B1

公开(公告)日：2001-01-23

申请号：US09191236

申请日：1998-11-13

Applicant: Ronald A. Weimer ,  Avishai Kepten ,  Michael Sendler

Inventor： Ronald A. Weimer ,  Avishai Kepten ,  Michael Sendler

IPC: C23C1646

CPC classification number: H01L28/84 ,  C23C16/24 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/2022 ,  H01L21/3205 ,  H01L22/26 ,  Y10S148/003 ,  Y10S148/122 ,  Y10S438/964

Abstract: A method for reliably forming polysilicon of a desired surface roughness includes providing a layer of doped or undoped amorphous silicon on a substrate and heating said substrate while monitoring the emission of said substrate and comparing the monitored emission with an expected emission attributable to the heating regime employed. An increase in the monitored emission not attributable to the heating regime signals a transition of the layer of amorphous silicon to rough polysilicon. A decrease in the monitored emission not attributable to the heating regime signals a transition to smooth polysilicon. The increases and decreases in the monitored emission can be used to end the heating regime at the time at which the desired surface roughness of polysilicon is formed, or merely to passively monitor the process. The power supplied to heat the substrate to a desired temperature can also be monitored, in that a drop in required power is indicative of the formation of polysilicon. By selecting the degree of crystallinity of the layer of doped or undoped amorphous silicon on a substrate, the grain size of the resulting HSG polysilicon can be controlled.

Abstract translation: 可靠地形成期望表面粗糙度的多晶硅的方法包括在衬底上提供掺杂或未掺杂的非晶硅层并加热所述衬底，同时监测所述衬底的发射并将所监测的发射与可归因于所采用的加热方式的预期发射 。 不能归因于加热方式的监测发射的增加表明非晶硅层向粗多晶硅的转变。 不受加热制度影响的监测排放的减少表明向多晶硅平滑过渡。 监测发射的增加和减少可以用于在形成期望的多晶硅表面粗糙度的时候终止加热状态，或者仅仅被动地监视该过程。 为了将衬底加热到​​所需温度，提供的功率也可以被监测，因为所需功率的下降指示多晶硅的形成。 通过选择衬底上掺杂或未掺杂的非晶硅层的结晶度，可以控制得到的HSG多晶硅的晶粒尺寸。

公开(公告)号：US5505158A

公开(公告)日：1996-04-09

申请号：US334088

申请日：1994-11-04

Applicant: Thomas P. Thorpe, Jr. ,  Ronald A. Weimer

Inventor： Thomas P. Thorpe, Jr. ,  Ronald A. Weimer

IPC: C30B25/02 ,  C30B25/14

CPC classification number: C30B25/02 ,  C30B29/04

Abstract: A novel apparatus and method for the cyclic growth-etch deposition of diamond on a substrate by flame chemical vapor deposition (CVD) is developed. The cyclic growth-etch diamond deposition is accomplished by placing a suitable substrate to be coated under a CVD flame and providing a disk or face plate or other shapes having one or more teeth (or holes) wherein upon rotation of the disk, or face plate, or other shape, the teeth attached to the disk, or face plate, or other shape obstruct the path of the CVD flame from contacting the substrate at a desired time scale of .tau..sub.growth and t.sub.cycle to produce high quality (FWHM of 1-3.5 cm.sup.-1) diamond.

Abstract translation: 开发了通过火焰化学气相沉积（CVD）在金属基体上循环生长蚀刻沉积金刚石的新型设备和方法。 循环生长蚀刻金刚石沉积通过将待涂覆的合适基底放置在CVD火焰下并提供具有一个或多个齿（或孔）的盘或面板或其它形状，其中在圆盘或面板 或其他形状，附着到盘或面板或其它形状的牙齿阻碍CVD火焰的路径以期望的时间尺度的tau生长和tcycle与基底接触以产生高质量（FWHM为1-3.5 厘米-1）金刚石。

公开(公告)号：US08569130B2

公开(公告)日：2013-10-29

申请号：US13192763

申请日：2011-07-28

Applicant: James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

Inventor： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.

Abstract translation: 公开了在如此形成的具有气隙的存储器阵列和存储器阵列中形成气隙的方法。 一种这样的方法可以包括通过半导体上的电荷存储结构形成具有第一电介质的隔离区域，所述隔离区域延伸到半导体中; 在隔离区域和电荷存储结构上形成第二电介质; 并且在隔离区域中形成气隙，使得气隙通过电荷存储结构，并且第一电介质的厚度在气隙和第二电介质之间。

公开(公告)号：US20110147826A1

公开(公告)日：2011-06-23

申请号：US13039600

申请日：2011-03-03

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.

Abstract translation: 一些实施方案包括在形成非挥发性记忆体中使用聚硅氮烷的方法。 存储器单元可以是多级单元（MLC）。 聚硅氮烷可以通过热加工转化为氮化硅，二氧化硅或氮氧化硅，并暴露于含有氧和氮的一种或两种的环境中。 所述方法可以包括使用聚硅氮烷形成非易失性存储单元的电荷捕获层。 所述方法可以或另外包括使用聚硅氮烷形成非易失性存储单元的隔间介电材料。 一些实施例包括形成NAND存储器阵列的存储单元的方法。

公开(公告)号：US20100282164A1

公开(公告)日：2010-11-11

申请号：US12840153

申请日：2010-07-20

Applicant: Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

Inventor： Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

IPC: C23C16/00 ,  B05C11/00

CPC classification number: C23C16/00 ,  C23C16/46

Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

Abstract translation: 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US20080245301A1

公开(公告)日：2008-10-09

申请号：US12140438

申请日：2008-06-17

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: C23C16/00

CPC classification number: C23C16/45546 ,  C23C16/4557 ,  C23C16/45578

Abstract: The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.

Abstract translation: 本发明包括可以在原子层沉积或化学气相沉积期间使用的沉积方法和装置。 加热表面设置在半导体衬底的堆叠和前体入口之间，并且被配置为使得有问题的副反应发生在加热表面附近，而不是靠近半导体衬底。 前体入口可以是多个前体入口之一，并且加热的表面可以是多个加热表面中的一个。