公开(公告)号：US20190198415A1

公开(公告)日：2019-06-27

申请号：US16293936

申请日：2019-03-06

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Dong Seong OH ,  Si Hyeon GO

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L21/48 ,  H01L23/485

CPC分类号： H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/485 ,  H01L23/544 ,  H01L24/83 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2223/54486

摘要： A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.

公开(公告)号：US20180151465A1

公开(公告)日：2018-05-31

申请号：US15491025

申请日：2017-04-19

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Dong Seong OH ,  Si Hyeon GO

IPC分类号： H01L23/367 ,  H01L23/485 ,  H01L23/544 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/367 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/485 ,  H01L23/544 ,  H01L2223/5448

摘要： A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.

公开(公告)号：US20180102309A1

公开(公告)日：2018-04-12

申请号：US15831499

申请日：2017-12-05

申请人： Magnachip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Si Hyeon Go ,  Jun Young Heo ,  Moon Taek Sung ,  Dong Seong Oh

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L25/18

摘要： A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.

公开(公告)号：US20200312715A1

公开(公告)日：2020-10-01

申请号：US16526020

申请日：2019-07-30

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Jin Won JEONG ,  Byeung Soo SONG ,  Dong Ki SHIM ,  Jin Han BAE

IPC分类号： H01L21/78 ,  H01L21/768 ,  H01L23/00 ,  H01L21/304

摘要： A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.

公开(公告)号：US20190207005A1

公开(公告)日：2019-07-04

申请号：US16294338

申请日：2019-03-06

申请人： MagnaChip Semiconductor, Ltd.

发明人： Myung Ho PARK ,  Ul Kyu SEO ,  Young Ho SEO ,  Jae Sik CHOI

IPC分类号： H01L29/417 ,  H01L23/535 ,  H01L29/40 ,  H01L29/78 ,  H01L23/00

CPC分类号： H01L29/41741 ,  H01L23/535 ,  H01L24/05 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05093

摘要： The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.

公开(公告)号：US20190019871A1

公开(公告)日：2019-01-17

申请号：US15901235

申请日：2018-02-21

申请人： MagnaChip Semiconductor, Ltd.

发明人： Myung Ho PARK ,  Ul Kyu SEO ,  Young Ho SEO ,  Jae Sik CHOI

IPC分类号： H01L29/417 ,  H01L23/00 ,  H01L29/40 ,  H01L29/78 ,  H01L23/535

摘要： The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.

公开(公告)号：US20180233424A1

公开(公告)日：2018-08-16

申请号：US15869443

申请日：2018-01-12

申请人： Magnachip Semiconductor, Ltd.

发明人： Moon Taek SUNG ,  Jae Sik CHOI

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/36 ,  H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor package device includes a lead frame including a lead frame pad and lead frame leads, a semiconductor chip located on the lead frame pad, and a substrate located on the semiconductor chip, wherein the lead frame leads include first lead frame leads coupled to the lead frame pad and second lead frame leads separated from the lead frame pad and attached to a bottom surface of the substrate.