公开(公告)号：US20230386578A1

公开(公告)日：2023-11-30

申请号：US17825439

申请日：2022-05-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C16/34

CPC分类号： G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C16/3404

摘要： A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

公开(公告)号：US11756597B2

公开(公告)日：2023-09-12

申请号：US17393112

申请日：2021-08-03

申请人： Micron Technology, Inc.

发明人： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC分类号： G11C7/20 ,  G11C5/14 ,  G11C11/4096 ,  G11C7/10

CPC分类号： G11C7/20 ,  G11C5/148 ,  G11C7/1063 ,  G11C11/4096

摘要： A system includes a memory device having memory cells and a processing device operatively coupled to the memory device. The processing device is to perform operations including: determining a length of time the memory device has been powered off; and in response to determining that the length of time satisfies a threshold value: for each of multiple groups of memory cells, asserting a corresponding flag; determining, based on the length of time, one or more adjusted demarcation voltages to be used in reading a state of the multiple groups of memory cells; and storing the one or more adjusted demarcation voltages for use in performing memory operations.

公开(公告)号：US20230062213A1

公开(公告)日：2023-03-02

申请号：US17961193

申请日：2022-10-06

申请人： Micron Technology, Inc.

发明人： Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC分类号： G11C29/10

摘要： A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values for seasoning operations by modifying a first trim value of the baseline trim values; causing each memory sub-system of a plurality of memory sub-systems to perform seasoning operations using the first modified set of trim values; responsive to determining that a memory sub-system of the plurality of memory sub-system failed to satisfy a predetermined criterion, determining whether the memory sub-system is extrinsically defective; responsive to determining that the memory sub-system is extrinsically defective, removing the extrinsically defective memory sub-system from the set of memory sub-systems; and generating a second modified set of trim values for seasoning operations.

公开(公告)号：US11500588B2

公开(公告)日：2022-11-15

申请号：US17147126

申请日：2021-01-12

申请人： Micron Technology, Inc.

发明人： Murong Lang ,  Zhenming Zhou

IPC分类号： G06F12/00 ,  G06F3/06 ,  G11C7/22

摘要： A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slope value represents a change of a read voltage level as a function of a delay time of a memory sub-system. Using the data structure, a stored slope value corresponding to a measured die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value. The read command is executed using the adjusted read voltage level.

公开(公告)号：US20220334961A1

公开(公告)日：2022-10-20

申请号：US17854797

申请日：2022-06-30

申请人： MICRON TECHNOLOGY, INC.

发明人： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC分类号： G06F12/02 ,  G06F11/07 ,  G06F11/30

摘要： A scaling factor for a data unit of a memory device is obtained. The scaling factor corresponds to a difference between a first error rate associated with a first set of memory access operations performed at the data unit and a second error rate associated with a second set of memory access operations performed at the data unit. A media management operation is scheduled on the data unit in view of the scaling factor.

公开(公告)号：US20220229603A1

公开(公告)日：2022-07-21

申请号：US17716689

申请日：2022-04-08

申请人： Micron Technology, Inc.

发明人： Murong Lang ,  Zhenming Zhou

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C7/22

摘要： A data structure including a target read voltage level corresponding to each set of values of a plurality of sets of values corresponding to a plurality of operating characteristics is stored. In response to a read command associated with a memory cell, a current set of measured values of the plurality of operating characteristics associated with the memory cell is measured. A match between a first set of values of the plurality of sets of values corresponding to the plurality of operating characteristics and the current set of measured values is identified. Using the data structure, a first stored target read voltage level corresponding to the match between the first set of values and the current set of measured values is identified. The read command is executed using the first stored target read voltage level.

公开(公告)号：US20220115084A1

公开(公告)日：2022-04-14

申请号：US17557782

申请日：2021-12-21

申请人： MICRON TECHNOLOGY, INC.

发明人： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC分类号： G11C29/50 ,  G11C29/44 ,  G11C29/12 ,  G11C16/26 ,  G11C16/10

摘要： A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

公开(公告)号：US20210132867A1

公开(公告)日：2021-05-06

申请号：US17147126

申请日：2021-01-12

申请人： Micron Technology, Inc.

发明人： Murong Lang ,  Zhenming Zhou

IPC分类号： G06F3/06 ,  G11C7/22

摘要： A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slope value represents a change of a read voltage level as a function of a delay time of a memory sub-system. Using the data structure, a stored slope value corresponding to a measured die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value. The read command is executed using the adjusted read voltage level.

公开(公告)号：US20210064277A1

公开(公告)日：2021-03-04

申请号：US16552165

申请日：2019-08-27

申请人： Micron Technology, Inc.

发明人： Murong Lang ,  Zhenming Zhou

IPC分类号： G06F3/06 ,  G11C7/22 ,  G11C7/10

摘要： Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.

公开(公告)号：US10790036B1

公开(公告)日：2020-09-29

申请号：US16553942

申请日：2019-08-28

申请人： Micron Technology, Inc.

发明人： Zhenming Zhou ,  Murong Lang

IPC分类号： G11C7/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  G11C16/10 ,  G11C13/00 ,  G11C29/50

摘要： A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. A plurality of test demarcation voltages is determined based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell. For each test demarcation voltage, an error rate of reading the state of the memory cell based on a respective test demarcation voltage is determined. A test demarcation voltage having the lowest error rate from the plurality of test demarcation voltages is determined. The current demarcation voltage is set to correspond to the test demarcation voltage having the lowest error rate.