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    PACKAGE-LEVEL ESD PROTECTION
    11.
    发明申请
    PACKAGE-LEVEL ESD PROTECTION 有权

    公开(公告)号：US20230138324A1

    公开(公告)日：2023-05-04

    申请号：US17902912

    申请日：2022-09-05

    Applicant: MEDIATEK INC.

    Inventor： Yu-Cheng Liao ,  Bo-Shih Huang ,  Che-Yuan Jao ,  Yi-Chieh Lin

    IPC: H01L23/60 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

    Abstract: The present invention provides a package including a first pad, a die and at least one package ESD component is disclosed. The first pad is configured to receive a signal from a device external to the package. The die comprises a second pad and an internal circuit, wherein the internal circuit is configured to receive the signal from the first pad via the second pad. The at least one ESD component is positioned outside the die.

    Electrostatic discharge (ESD) protection device
    12.
    发明授权
    Electrostatic discharge (ESD) protection device 有权

    公开(公告)号：US10236285B2

    公开(公告)日：2019-03-19

    申请号：US15495185

    申请日：2017-04-24

    Applicant: MediaTek Inc.

    Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Bo-Shih Huang ,  Chang-Tzu Wang

    IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

    Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

    ESD protection circuit
    14.
    发明授权
    ESD protection circuit 有权
    ESD保护电路

    公开(公告)号：US09331472B2

    公开(公告)日：2016-05-03

    申请号：US14591254

    申请日：2015-01-07

    Applicant: MediaTek Inc

    Inventor： Bo-Shih Huang ,  Tsung-Ming Chen ,  Yuan-Hung Chung

    IPC: H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

    CPC classification number: H02H3/20 ,  H02H9/046

    Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line, wherein no ESD current flows through the impedance device when an ESD event occurs at the pad.

    Abstract translation: 提供静电放电（ESD）保护电路。 ESD保护电路包括耦合在焊盘和电源线之间的阻抗装置以及耦合在焊盘和接地线之间的夹紧单元，其中当在焊盘处发生ESD事件时，ESD电流不流过阻抗器件。

    ESD PROTECTING CIRCUIT
    15.
    发明申请
    ESD PROTECTING CIRCUIT 有权
    ESD保护电路

    公开(公告)号：US20160064926A1

    公开(公告)日：2016-03-03

    申请号：US14936685

    申请日：2015-11-10

    Applicant: MEDIATEK INC.

    Inventor： Bo-Shih Huang

    IPC: H02H9/04

    CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H02H9/046

    Abstract: An ESD protecting circuit comprising: a first and a second voltage pad; an I/O pad; a first ESD protecting module, comprising a first terminal coupled to the first voltage pad, and comprising a second terminal; a switch, comprising a first terminal coupled to the second terminal of the first ESD protecting module, comprising a second terminal coupled to the I/O pad, and comprising a control terminal for receiving a control signal; a second ESD protecting module, comprising a first terminal coupled to the first terminal of the MOS transistor, and comprising a second terminal coupled to the second voltage pad; and an ESD detecting circuit, for detecting if an ESD voltage exists, for generating the control signal to control the MOS transistor to be conductive when an ESD voltage is detected and to control the MOS transistor to be nonconductive when the ESD voltage is not detected.

    Abstract translation: 一种ESD保护电路，包括：第一和第二电压焊盘; 一个I / O焊盘; 第一ESD保护模块，包括耦合到所述第一电压焊盘的第一端子，并且包括第二端子; 开关，包括耦合到第一ESD保护模块的第二端子的第一端子，包括耦合到I / O焊盘的第二端子，并且包括用于接收控制信号的控制端子; 第二ESD保护模块，包括耦合到所述MOS晶体管的所述第一端子的第一端子，并且包括耦合到所述第二电压焊盘的第二端子; 以及用于检测ESD电压是否存在的ESD检测电路，用于当检测到ESD电压时产生用于控制MOS晶体管导通的控制信号，并且在未检测到ESD电压时控制MOS晶体管为非导通。

    TWO-DIMENSIONAL POWER CLAMP CELL
    16.
    发明公开
    TWO-DIMENSIONAL POWER CLAMP CELL 审中-公开

    公开(公告)号：US20240332286A1

    公开(公告)日：2024-10-03

    申请号：US18593962

    申请日：2024-03-03

    Applicant: MEDIATEK INC.

    Inventor： Yung-Ju Wen ,  Bo-Shih Huang

    IPC: H01L27/02 ,  G05F1/569

    CPC classification number: H01L27/0266 ,  G05F1/569 ,  H01L27/0292 ,  H01L27/0296

    Abstract: The present invention provides a power clamp cell including a power clamping circuit, a power routing and a global routing is disclosed. The power routing has at least a first vertical metal line and a first horizontal metal line, and the power routing is implemented by using a first metal layer in semiconductor process. The ground routing has at least a second vertical metal line and a second horizontal metal line, and the ground routing is implemented by using a second metal layer in the semiconductor process.

    ESD DETECTION CIRCUIT
    18.
    发明申请
    ESD DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20170093152A1

    公开(公告)日：2017-03-30

    申请号：US15271268

    申请日：2016-09-21

    Applicant: MEDIATEK Inc.

    Inventor： Che-Yuan Jao ,  Bo-Shih Huang

    IPC: H02H9/04

    CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/14

    Abstract: An ESD protected IC includes: at least one functional circuitry, coupled to a first voltage supply and a second voltage supply, the functional circuitry including at least one functional package ball; and at least one ESD detection circuit, coupled to the second voltage supply, the ESD detection circuit free of being coupled to the first voltage supply, and further free of being coupled to the functional package ball of the functional circuitry.

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