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    Ion to neutral control for wafer processing with dual plasma source reactor
    11.
    发明授权
    Ion to neutral control for wafer processing with dual plasma source reactor 有权

    公开(公告)号：US09793126B2

    公开(公告)日：2017-10-17

    申请号：US14033241

    申请日：2013-09-20

    申请人： Lam Research Corporation

    发明人： Rajinder Dhindsa ,  Sang Ki Nam ,  Alexei Marakhtanov ,  Eric A. Hudson

    IPC分类号： C23C14/34 ,  H01L21/3065 ,  H01J37/32

    CPC分类号： H01L21/67069 ,  H01J37/32357 ,  H01J37/32422 ,  H01J2237/334 ,  H01L21/3065

    摘要： The disclosed techniques relate to methods and apparatus for etching a substrate. A plate assembly divides a reaction chamber into a lower and upper sub-chamber. The plate assembly includes an upper and lower plate having apertures therethrough. When the apertures in the upper and lower plates are aligned, ions and neutral species may travel through the plate assembly into the lower sub-chamber. When the apertures are not aligned, ions are prevented from passing through the assembly while neutral species are much less affected. Thus, the ratio of ion flux:neutral flux may be tuned by controlling the amount of area over which the apertures are aligned. In certain embodiments, one plate of the plate assembly is implemented as a series of concentric, independently movable injection control rings. Further, in some embodiments, the upper sub-chamber is implemented as a series of concentric plasma zones separated by walls of insulating material.

    ION TO NEUTRAL CONTROL FOR WAFER PROCESSING WITH DUAL PLASMA SOURCE REACTOR
    12.
    发明申请
    ION TO NEUTRAL CONTROL FOR WAFER PROCESSING WITH DUAL PLASMA SOURCE REACTOR 有权

    公开(公告)号：US20170213747A9

    公开(公告)日：2017-07-27

    申请号：US14033241

    申请日：2013-09-20

    申请人： Lam Research Corporation

    发明人： Rajinder Dhindsa ,  Sang Ki Nam ,  Alexei Marakhtanov ,  Eric A. Hudson

    IPC分类号： H01L21/67 ,  H01L21/3065

    CPC分类号： H01L21/67069 ,  H01J37/32357 ,  H01J37/32422 ,  H01J2237/334 ,  H01L21/3065

    摘要： The disclosed techniques relate to methods and apparatus for etching a substrate. A plate assembly divides a reaction chamber into a lower and upper sub-chamber. The plate assembly includes an upper and lower plate having apertures therethrough. When the apertures in the upper and lower plates are aligned, ions and neutral species may travel through the plate assembly into the lower sub-chamber. When the apertures are not aligned, ions are prevented from passing through the assembly while neutral species are much less affected. Thus, the ratio of ion flux:neutral flux may be tuned by controlling the amount of area over which the apertures are aligned. In certain embodiments, one plate of the plate assembly is implemented as a series of concentric, independently movable injection control rings. Further, in some embodiments, the upper sub-chamber is implemented as a series of concentric plasma zones separated by walls of insulating material.

    MASK SHRINK LAYER FOR HIGH ASPECT RATIO DIELECTRIC ETCH
    13.
    发明申请
    MASK SHRINK LAYER FOR HIGH ASPECT RATIO DIELECTRIC ETCH 审中-公开
    用于高比例电介质蚀刻的掩模层

    公开(公告)号：US20170076945A1

    公开(公告)日：2017-03-16

    申请号：US15359362

    申请日：2016-11-22

    申请人： Lam Research Corporation

    发明人： Eric A. Hudson ,  Mark H. Wilcoxson ,  Kalman Pelhos ,  Hyunjong Shim ,  Merrett Wong

    IPC分类号： H01L21/033 ,  H01L21/67 ,  H01J37/32 ,  H01L21/311

    CPC分类号： H01L21/0338 ,  H01J37/32091 ,  H01J37/32366 ,  H01J37/3244 ,  H01J37/32568 ,  H01J37/32715 ,  H01J37/32733 ,  H01J37/32908 ,  H01J2237/334 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/67069 ,  H01L21/6719 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67745

    摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.

    摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质堆叠中形成凹陷特征的方法，装置和系统。 在许多实施例中，掩模收缩层沉积在图案化掩模层上，从而使掩模层中的开口变窄。 掩模收缩层可通过包括但不限于原子层沉积或化学气相沉积的气相沉积工艺沉积。 掩模收缩层可以导致较窄的，更垂直均匀的蚀刻特征。 在一些实施例中，在单个蚀刻步骤中完成蚀刻。 在一些其它实施例中，蚀刻可以分阶段进行，循环使用沉积步骤设计成在部分蚀刻的特征上沉积保护性侧壁涂层。 含金属膜特别适合作为掩模收缩膜和保护性侧壁涂层。

    Technique to deposit sidewall passivation for high aspect ratio cylinder etch
    16.
    发明授权
    Technique to deposit sidewall passivation for high aspect ratio cylinder etch 有权
    沉积用于高纵横比圆柱体蚀刻的侧壁钝化的技术

    公开(公告)号：US09378971B1

    公开(公告)日：2016-06-28

    申请号：US14560414

    申请日：2014-12-04

    申请人： Lam Research Corporation

    发明人： Joseph Scott Briggs ,  Eric A. Hudson

    IPC分类号： H01L21/3065 ,  C23C16/52 ,  C23C16/50 ,  C23C16/455 ,  H01J37/32 ,  H01L21/02

    CPC分类号： H01L21/31116 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32513 ,  H01J37/32577 ,  H01J37/32623 ,  H01J37/32651 ,  H01J37/32871 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/30655 ,  H01L27/108 ,  H01L27/115

    摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.

    摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质材料中形成凹陷特征的方法，装置和系统。 以循环方式采用分离的蚀刻和沉积操作。 每个蚀刻操作部分地蚀刻该特征。 每个沉积操作在特征的侧壁上形成保护涂层，以防止在蚀刻操作期间电介质材料的横向蚀刻。 保护涂层可以使用沿着侧壁的大致整个长度形成保护涂层的方法进行沉积。 在一些实施方案中，可以使用具有低粘附系数的特定反应物来沉积保护性涂层。 保护涂层也可以使用特定的反应机理沉积，这导致基本上完全的侧壁涂覆。 在一些情况下，使用等离子体辅助原子层沉积或等离子体辅助化学气相沉积来沉积保护涂层。

    SYSTEM, METHOD AND APPARATUS FOR PLASMA ETCH HAVING INDEPENDENT CONTROL OF ION GENERATION AND DISSOCIATION OF PROCESS GAS
    18.
    发明申请
    SYSTEM, METHOD AND APPARATUS FOR PLASMA ETCH HAVING INDEPENDENT CONTROL OF ION GENERATION AND DISSOCIATION OF PROCESS GAS 审中-公开
    具有离子发生和过程气体分离独立控制的等离子体蚀刻的系统，方法和装置

    公开(公告)号：US20160049304A1

    公开(公告)日：2016-02-18

    申请号：US14924572

    申请日：2015-10-27

    申请人： Lam Research Corporation

    发明人： Eric A. Hudson

    IPC分类号： H01L21/3065

    CPC分类号： H01L21/3065 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32596 ,  H01J2237/182 ,  H01L21/31116 ,  H05H1/24

    摘要： A method of etching a wafer includes injecting a source gas mixture into a process chamber. The injecting includes injecting the source gas into multiple hollow cathode cavities in a top electrode, generating plasma in each of the cavities, and outputting the plasma from corresponding outlets of the cavities into a wafer processing region in the chamber, where the processing region is located between the outlets and a surface to be etched. An etchant gas mixture is injected into the processing region through injection ports in the top electrode such that the etchant gas mixes with the plasma output from the outlets. The etchant gas is prevented from flowing into the outlets of the cavities by the plasma flowing from the outlets. Mixing the etchant gas and the output from the cavities generates a desired chemical species in the processing region and thereby enables the surface to be etched.

    摘要翻译： 蚀刻晶片的方法包括将源气体混合物注入处理室。 注入包括将源气体注入到顶部电极中的多个空心阴极腔中，在每个空腔中产生等离子体，并将等离子体从空腔的相应出口输出到处理区域所在的腔室中的晶片处理区域 在出口和待蚀刻的表面之间。 蚀刻剂气体混合物通过顶部电极中的注入口注入到处理区域中，使得蚀刻剂气体与来自出口的等离子体输出混合。 通过从出口流出的等离子体，防止蚀刻剂气体流入空腔的出口。 将蚀刻剂气体和空腔的输出混合在处理区域中产生期望的化学物质，从而使表面能够被蚀刻。