公开(公告)号：US20090206464A1

公开(公告)日：2009-08-20

申请号：US12432003

申请日：2009-04-29

Applicant: Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract translation: 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20090186777A1

公开(公告)日：2009-07-23

申请号：US12357270

申请日：2009-01-21

Applicant: June-Young LEE ,  Dong-Ho LEE ,  Jae-Young KIM

Inventor： June-Young LEE ,  Dong-Ho LEE ,  Jae-Young KIM

IPC: C40B40/04

CPC classification number: C40B99/00 ,  B01J19/0046 ,  B01J2219/00317 ,  B01J2219/00527 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00617 ,  B01J2219/00621 ,  B01J2219/00626 ,  B01J2219/00637 ,  B01J2219/00659 ,  B01J2219/00662 ,  B01J2219/0072 ,  B01L3/5085 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/0636 ,  B01L2300/0829 ,  B01L2300/0893

Abstract: A biochip can include a substrate having surface features of protrusions or recesses and probes coupled to each of the surface features. A biochip can include a substrate having recess regions and probes coupled to each of the recess regions, wherein a surface of each of the recess regions has convexes and concaves. A biochip can include a substrate having recess regions, immobilization layers conformally formed in the recess regions, and probes coupled onto each of the immobilization layers. The biochip can be divided into probe cell regions to which the probes are coupled, wherein the recess regions are formed in the probe cell regions, and non-probe cell regions, wherein a surface of each of the non-probe cell regions can include an exposed surface of the substrate.

Abstract translation: 生物芯片可以包括具有突起或凹陷的表面特征的基底和耦合到每个表面特征的探针。 生物芯片可以包括具有凹陷区域的衬底和耦合到每个凹陷区域的探针，其中每个凹陷区域的表面具有凸起和凹陷。 生物芯片可以包括具有凹陷区域的基底，在凹陷区域中保形地形成的固定层，以及耦合到每个固定层上的探针。 生物芯片可以分为与探针连接的探针细胞区域，其中在探针细胞区域中形成凹陷区域，以及非探针细胞区域，其中每个非探针细胞区域的表面可以包括 曝光的表面。

公开(公告)号：US20080179734A1

公开(公告)日：2008-07-31

申请号：US12018743

申请日：2008-01-23

Applicant: Yong-Chai KWON ,  Dong-Ho LEE ,  Sun-Won KANG

Inventor： Yong-Chai KWON ,  Dong-Ho LEE ,  Sun-Won KANG

IPC: H01L23/538 ,  H01L21/52

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stacked package includes a printed circuit board (PCB), a plurality of semiconductor chips, plugs and a controller. The semiconductor chips are sequentially stacked on the PCB. The plugs electrically connect each of the semiconductor chips to the PCB. The controller is disposed in any one of the semiconductor chips. The controller is electrically coupled to the plugs. Thus, the controller may be built in the semiconductor chip by a separate process so that a mechanical impact generated in a process for bonding the controller is not applied to the semiconductor chips. Further, a mechanical impact applied to the controller, which is generated in a process for forming a protection member, may be reduced.

Abstract translation: 堆叠式封装包括印刷电路板（PCB），多个半导体芯片，插头和控制器。 半导体芯片依次堆叠在PCB上。 插头将每个半导体芯片电连接到PCB。 控制器设置在任何一个半导体芯片中。 控制器电耦合到插头。 因此，可以通过单独的处理将控制器内置在半导体芯片中，使得在用于接合控制器的处理中产生的机械冲击不应用于半导体芯片。 此外，可以减少在形成保护构件的过程中产生的对控制器的机械冲击。

公开(公告)号：US20080088031A1

公开(公告)日：2008-04-17

申请号：US11866942

申请日：2007-10-03

Applicant: Yong-Chai KWON ,  Dong-Ho LEE

Inventor： Yong-Chai KWON ,  Dong-Ho LEE

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract translation: 公开了一种半导体封装结构及其制造方法。 制造半导体封装结构的方法可以表征为包括在半导体衬底上形成半导体芯片。 每个半导体芯片包括芯片焊盘。 通孔通过半导体芯片形成。 重新分配结构和芯片选择互连层形成在将通孔与芯片焊盘连接的半导体芯片上。 芯片选择互连层被图案化以在至少一个半导体芯片上形成具有不同结构的芯片选择互连线。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US20140290590A1

公开(公告)日：2014-10-02

申请号：US13850787

申请日：2013-03-26

Applicant: Sung-Hwan CHOI ,  Jin-Min CHOI ,  Dong-Ho LEE

Inventor： Sung-Hwan CHOI ,  Jin-Min CHOI ,  Dong-Ho LEE

IPC: F24H1/16

CPC classification number: F24H1/36 ,  F24H1/403 ,  F24H1/44 ,  F24H8/00 ,  Y02B30/102

Abstract: A condensing type hot water boiler comprises: a firebox casing that formulates a firebox in which fuel is combusted; a burner that ignites fuel furnished in the upper part of said firebox casing; a ventilator that supplies air to said firebox; a heat exchange casing, wherein heat is exchanged between hot water and the flame and combustion gas flowing in from said firebox, located at the lower part of said firebox casing; and a hot water coil formed to cover the inner wall of said firebox casing and in which hot water is received in the interior from said heat exchange casing for heat exchange with flame and combustion gas of the interior of said firebox.

Abstract translation: 一种冷凝式热水锅炉，包括：燃烧箱燃烧燃烧的火箱; 点燃燃料箱壳体上部的燃料的燃烧器; 一个向所述火箱提供空气的呼吸机; 热交换壳体，其中热量与来自位于所述火箱壳体下部的所述火箱的火焰和燃烧气体之间的热交换; 以及热水盘管，其形成为覆盖所述火箱壳体的内壁，并且其中热水从所述热交换壳体的内部接收以与所述火箱的内部的火焰和燃烧气体进行热交换。

公开(公告)号：US20090267211A1

公开(公告)日：2009-10-29

申请号：US12498913

申请日：2009-07-07

Applicant: Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US20090108432A1

公开(公告)日：2009-04-30

申请号：US12338905

申请日：2008-12-18

Applicant: Dong-Ho LEE

Inventor： Dong-Ho LEE

IPC: H01L23/498

CPC classification number: H01L25/105 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/15311

Abstract: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

Abstract translation: 通过堆叠至少两个区域阵列型芯片级封装件来制造本发明的堆叠封装。 相邻的一对芯片级封装的每个芯片级封装以上堆叠芯片级封装的焊盘焊盘与下堆叠芯片尺寸封装的方向相反的方式附接到另一芯片尺寸封装，并且电路 上堆叠芯片级封装的图案通过例如连接板电连接到下堆叠芯片级封装的图案。 因此，不仅可以堆叠扇出式芯片级封装，而且可以有效地堆叠普通区域阵列型芯片级封装。

公开(公告)号：US20080128905A1

公开(公告)日：2008-06-05

申请号：US11950251

申请日：2007-12-04

Applicant: In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

Inventor： In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract translation: 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US20080087974A1

公开(公告)日：2008-04-17

申请号：US11866940

申请日：2007-10-03

Applicant: Yong-Chai KWON ,  Dong-Ho LEE

Inventor： Yong-Chai KWON ,  Dong-Ho LEE

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.

Abstract translation: 提供了一种相机模块及其制造方法。 该方法包括制备包括上连接部分的透镜结构。 下连接部分形成在基板的预定区域中。 下连接部分分别限定芯片区域并配合在上连接部分中。 图像传感器芯片位于芯片区域的底表面上。 透镜结构使用上连接部分和下连接部分粘合到基板上。

公开(公告)号：US20070267738A1

公开(公告)日：2007-11-22

申请号：US11751464

申请日：2007-05-21

Applicant: Hyun-Soo CHUNG ,  Cha-Jea JO ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  Cha-Jea JO ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L23/34 ,  H01L21/00

CPC classification number: H01L23/473 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.

Abstract translation: 提供了在其底面上具有冷却路径的半导体器件。 具有冷却路径的叠层型半导体器件包括：堆叠型半导体芯片，包括第一半导体芯片和第二半导体芯片。 第一半导体芯片包括其中形成有电路单元的第一表面和形成有第一冷却路径的第二表面，并且第二半导体芯片包括其中形成电路单元的第一表面和第二表面，其中第二表面 形成第二冷却路径。 第一半导体芯片的第二表面和第二半导体芯片的第二表面彼此接合，并且使用第一和第二冷却路径在堆叠型半导体芯片的中间形成第三冷却路径。 堆叠型半导体器件的翘曲被抑制，并且易于散热。