公开(公告)号：US20240096791A1

公开(公告)日：2024-03-21

申请号：US18520872

申请日：2023-11-28

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro J. Kobrinsky ,  Marni Nabors

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L23/528 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3128 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L23/5226

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

公开(公告)号：US11410928B2

公开(公告)日：2022-08-09

申请号：US16003031

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro Kobrinsky ,  Marni Nabors

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/522 ,  H01L23/00

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

公开(公告)号：US11387198B2

公开(公告)日：2022-07-12

申请号：US16635536

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Doug Ingerly ,  Rajesh Kumar ,  Harish Krishnamurthy ,  Nachiket Venkappayya Desai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US11249113B2

公开(公告)日：2022-02-15

申请号：US17111298

申请日：2020-12-03

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/48 ,  H01L23/32 ,  H01L21/48 ,  H01L21/027 ,  G01R31/28 ,  H01L23/14

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20200025801A1

公开(公告)日：2020-01-23

申请号：US16586763

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/14 ,  G01R31/28 ,  H01L21/027 ,  H01L21/48 ,  H01L23/32 ,  H01L23/48

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US10192783B2

公开(公告)日：2019-01-29

申请号：US15266819

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

IPC: H01L21/70 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

公开(公告)号：US09831306B2

公开(公告)日：2017-11-28

申请号：US15024750

申请日：2013-12-19

Applicant: INTEL CORPORATION

Inventor： Milton Clair Webb ,  Mark Bohr ,  Tahir Ghani ,  Szuya S. Liao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US12100705B2

公开(公告)日：2024-09-24

申请号：US17825664

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Yih Wang ,  Rishabh Mehandru ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Mark Bohr ,  Marni Nabors

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/76877 ,  H01L21/823431 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US11830829B2

公开(公告)日：2023-11-28

申请号：US17836117

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Doug Ingerly ,  Rajesh Kumar ,  Harish Krishnamurthy ,  Nachiket Venkappayya Desai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2924/19042

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US11373987B2

公开(公告)日：2022-06-28

申请号：US16646460

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Glenn J. Hinton ,  Rajesh Kumar

IPC: H01L21/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.