公开(公告)号：US09496486B2

公开(公告)日：2016-11-15

申请号：US14812655

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

公开(公告)号：US10192783B2

公开(公告)日：2019-01-29

申请号：US15266819

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

IPC: H01L21/70 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

公开(公告)号：US11004739B2

公开(公告)日：2021-05-11

申请号：US16219795

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.