公开(公告)号：US20240088199A1

公开(公告)日：2024-03-14

申请号：US17943354

申请日：2022-09-13

申请人： Intel Corporation

发明人： Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Jeremy D. Ecton ,  Mohammad Rahman ,  Gang Duan

IPC分类号： H01L49/02 ,  H01F27/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC分类号： H01L28/10 ,  H01F27/292 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18

摘要： Techniques for a glass core inductor are disclosed. In the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (FIVR). The FIVR includes a glass core inductor that is embedded in the glass substrate. Each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. The inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.

公开(公告)号：US20230395467A1

公开(公告)日：2023-12-07

申请号：US17833648

申请日：2022-06-06

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/03

CPC分类号： H01L23/481 ,  H01L23/49822 ,  H01L23/49816 ,  H01L21/486 ,  H01L21/76898 ,  H05K1/112 ,  H01L24/16 ,  H05K3/429 ,  H05K3/4644 ,  H05K1/0306 ,  H01L2224/16225

摘要： In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US20230076917A1

公开(公告)日：2023-03-09

申请号：US17470684

申请日：2021-09-09

申请人： Intel Corporation

发明人： Hiroki Tanaka ,  Brandon C. Marin ,  Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Jeremy D. Ecton ,  Hari Mahalingam ,  Benjamin Duong

IPC分类号： G02F1/035

摘要： An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

公开(公告)号：US20240222249A1

公开(公告)日：2024-07-04

申请号：US18148355

申请日：2022-12-29

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Srinivas V. Pietambaram ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Oladeji T. Fadayomi ,  Manuel Gadogbe ,  Matthew L. Tingey

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

摘要： In one embodiment, an integrated circuit package substrate includes a glass layer having at least one roughened surface (e.g., with an average roughness above 100 nm) and a metal (e.g., a metal trace or metal via) in contact with the roughened surface of the glass layer.

公开(公告)号：US20240222248A1

公开(公告)日：2024-07-04

申请号：US18147457

申请日：2022-12-28

申请人： Intel Corporation

发明人： Brandon Christian Marin ,  Sashi Shekhar Kandanur ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy D. Ecton

IPC分类号： H01L23/498 ,  H01L21/306

CPC分类号： H01L23/49827 ,  H01L21/30604 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/78

摘要： Architectures and methods for metal lamination on a glass layer or glass core. The architectures implement dummy anchors to prevent or reduce the delamination of conductive materials from glass surfaces. The anchors hold the conductive pads and conductive material planes down to the glass surface. The architecture includes various combinations of end anchors and through glass via (TGV) anchors.

公开(公告)号：US20240213169A1

公开(公告)日：2024-06-27

申请号：US18086265

申请日：2022-12-21

申请人： Intel Corporation

发明人： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/64 ,  H10B80/00

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5382 ,  H01L23/5386 ,  H01L23/645 ,  H10B80/00 ,  H01L24/32

摘要： An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.

公开(公告)号：US20240176084A1

公开(公告)日：2024-05-30

申请号：US18059923

申请日：2022-11-29

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Srinivas V. Pietambaram ,  Brandon Christian Marin ,  Gang Duan ,  Bai Nie

IPC分类号： G02B6/42

CPC分类号： G02B6/428 ,  G02B6/136

摘要： A PIC first patch architecture includes a solderless electrical connection at a die interconnect surface. Redistribution layers (RDLs) are patterned onto a face of an integrated circuit (IC) die and photonic integrated circuit (PIC) die prior to placement of the RDLs into a cavity in a glass layer. Optical interconnections for the PIC die are protected during RDL patterning and optical waveguides may be patterned into the glass layer fore or after assembling the PIC first patch including the RDL and glass layer.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

摘要： A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US11670504B2

公开(公告)日：2023-06-06

申请号：US16419426

申请日：2019-05-22

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Brandon C. Marin ,  Andrew J. Brown ,  Dilan Seneviratne

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L49/02

CPC分类号： H01L21/02345 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02194 ,  H01L21/76825 ,  H01L21/76841 ,  H01L23/5329 ,  H01L23/53228 ,  H01L28/60

摘要： A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 μm in thickness, and a second electrode is over the cured PID.

公开(公告)号：US20220406618A1

公开(公告)日：2022-12-22

申请号：US17351537

申请日：2021-06-18

申请人： Intel Corporation

发明人： Changhua Liu ,  Leonel R. Arana ,  Jeremy D. Ecton ,  Suddhasattwa Nad ,  Brandon Christian Marin

IPC分类号： H01L21/48 ,  H01L23/538 ,  H01L21/768

摘要： Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.