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    Dual/multi-mode processor pipeline sampling
    13.
    发明授权
    Dual/multi-mode processor pipeline sampling 有权

    公开(公告)号：US10176013B2

    公开(公告)日：2019-01-08

    申请号：US14208257

    申请日：2014-03-13

    Applicant: International Business Machines Corporation

    Inventor： Deanna Postles Dunn Berger ,  Kathryn M. Jackson ,  Joshua D. Massover ,  Gary E. Strait ,  Hanno Ulrich ,  Craig R. Walters

    IPC: G06F11/30 ,  G06F9/48 ,  G06F11/34

    Abstract: Embodiments are directed to systems and methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

    INCREASED BANDWIDTH OF ORDERED STORES IN A NON-UNIFORM MEMORY SUBSYSTEM
    16.
    发明申请
    INCREASED BANDWIDTH OF ORDERED STORES IN A NON-UNIFORM MEMORY SUBSYSTEM 审中-公开
    非均匀存储器子系统中有序存储的带宽增加

    公开(公告)号：US20160124854A1

    公开(公告)日：2016-05-05

    申请号：US14533579

    申请日：2014-11-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ekaterina M. Ambroladze ,  Garrett M. Drapala ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Gary E. Strait

    IPC: G06F12/08 ,  G06F13/42

    CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0842 ,  G06F13/4221 ,  G06F2212/271 ,  G06F2212/604

    Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

    Abstract translation: 一种方法，计算机程序产品和系统，用于维持包括两个或多个顺序排列的存储器的数据流的正确排序，所述数据流被移动到目的地存储器设备，所述两个或多个顺序排序的存储器至少包括第一 存储和第二存储，其中第一存储被目的地存储设备拒绝。 计算机实现的方法包括将第一存储发送到目的地存储设备。 将条件请求发送到目的地存储器设备以批准将第二存储发送到目的地存储器设备，该条件请求取决于第一存储器的成功完成。 响应于接收到对应于第一商店的拒绝响应，第二商店被取消。

    MATRIX AND COMPRESSION-BASED ERROR DETECTION
    17.
    发明申请
    MATRIX AND COMPRESSION-BASED ERROR DETECTION 有权

    公开(公告)号：US20150261638A1

    公开(公告)日：2015-09-17

    申请号：US14501676

    申请日：2014-09-30

    Applicant: International Business Machines Corporation

    Inventor： Garrett M. Drapala ,  Gary E. Strait

    IPC: G06F11/273

    CPC classification number: G11C29/04 ,  G06F11/273 ,  G11C29/12 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

    Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.

    DUAL/MULTI-MODE PROCESSOR PIPELINE SAMPLING
    18.
    发明申请
    DUAL/MULTI-MODE PROCESSOR PIPELINE SAMPLING 审中-公开
    双/多模式处理器管道采样

    公开(公告)号：US20150261533A1

    公开(公告)日：2015-09-17

    申请号：US14501190

    申请日：2014-09-30

    Applicant: International Business Machines Corporation

    Inventor： Deanna Postles Dunn Berger ,  Kathryn M. Jackson ,  Joshua D. Massover ,  Gary E. Strait ,  Hanno Ulrich ,  Craig R. Walters

    IPC: G06F9/30

    CPC classification number: G06F9/4881 ,  G06F11/30 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3409 ,  G06F11/3476 ,  G06F11/348

    Abstract: Embodiments are directed to methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

    Abstract translation: 实施例涉及用于通过流水线分析算法有效地采样数据进行分析的方法。 如果在采样时间内主体管线不活动，则采样数据的数量最大化，而不会通过采样“非流水线活动”数据而增加采样开销。 选择非流水线活动数据以包括与主体管线的性能相关的整体系统信息，但不一定取决于主体流水线是否活动。 在一些实施例中，非流水线活动数据允许确认流水线性能特征，否则在流水线活动时，必须由随后的流水线分析算法从采样的数据中推断。 在一些实施例中，非流水线活动数据允许流水线分析算法分析在流水线处于活动状态时所采样的数据不能被推断的附加性能特征。

    Bad wordline/array detection in memory
    19.
    发明授权
    Bad wordline/array detection in memory 有权
    内存中的字线/阵列检测不良

    公开(公告)号：US09065481B2

    公开(公告)日：2015-06-23

    申请号：US13747842

    申请日：2013-01-23

    Applicant: International Business Machines Corporation

    Inventor： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

    IPC: G11C29/00 ,  H03M13/05 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20

    CPC classification number: H03M13/05 ,  G06F11/073 ,  G06F11/1008 ,  G06F11/1064 ,  G06F11/1666 ,  G06F11/20

    Abstract: A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

    Abstract translation: 提供了一种错误检测技术。 控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。 控制器检测读取的字线的ECC字中的错误。 控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。 控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

    BAD WORDLINE/ARRAY DETECTION IN MEMORY
    20.
    发明申请
    BAD WORDLINE/ARRAY DETECTION IN MEMORY 有权
    BAD WORDLINE /阵列检测记忆

    公开(公告)号：US20130339823A1

    公开(公告)日：2013-12-19

    申请号：US13747842

    申请日：2013-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

    IPC: H03M13/05

    CPC classification number: H03M13/05 ,  G06F11/073 ,  G06F11/1008 ,  G06F11/1064 ,  G06F11/1666 ,  G06F11/20

    Abstract: A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

    Abstract translation: 提供了一种错误检测技术。 控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。 控制器检测读取的字线的ECC字中的错误。 控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。 控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

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