公开(公告)号：US09378785B2

公开(公告)日：2016-06-28

申请号：US13974001

申请日：2013-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-He Lin ,  Sih-Han Li ,  Wen-Pin Lin ,  Shyh-Shyuan Sheu

IPC: G11C11/00 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C7/1072 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract translation: 电阻式随机存取存储器件包括存储器阵列，读取电路，回写逻辑电路和回写电路。 读取电路读取存储在所选择的存储器单元中的数据，并且相应地产生第一控制信号。 回写逻辑电路根据第一控制信号和第二控制信号产生回写控制信号。 回写电路根据回写控制信号和回写电压对所选择的存储单元执行写回操作，以将所选存储单元的电阻状态从低电阻状态改变为 并且根据所选存储单元的电阻状态产生第二控制信号。

公开(公告)号：US20180136010A1

公开(公告)日：2018-05-17

申请号：US15607389

申请日：2017-05-26

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shyh-Shyuan Sheu ,  Ya-Wen Yang ,  Chih-Ping Cheng ,  Chih-Sheng Lin

IPC: G01D3/02 ,  H03K17/30 ,  G01D18/00

CPC classification number: G01D3/022 ,  G01B2210/60 ,  G01D18/008 ,  H03K17/30

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

公开(公告)号：US08942027B1

公开(公告)日：2015-01-27

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C11/00 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US20150016176A1

公开(公告)日：2015-01-15

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US10324054B2

公开(公告)日：2019-06-18

申请号：US16178599

申请日：2018-11-02

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

公开(公告)号：US20190154473A1

公开(公告)日：2019-05-23

申请号：US15851609

申请日：2017-12-21

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01D18/00

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

公开(公告)号：US10101175B2

公开(公告)日：2018-10-16

申请号：US15607389

申请日：2017-05-26

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shyh-Shyuan Sheu ,  Ya-Wen Yang ,  Chih-Ping Cheng ,  Chih-Sheng Lin

IPC: G01D3/02 ,  G01D18/00 ,  H03K17/30

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

公开(公告)号：US09887007B1

公开(公告)日：2018-02-06

申请号：US15381703

申请日：2016-12-16

Applicant: Industrial Technology Research Institute

Inventor： Chia-Chen Kuo ,  Shyh-Shyuan Sheu

IPC: G11C5/06 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0061 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A variable-resistance memory and a writing method thereof are provided. The variable-resistance memory includes a variable-resistance memory cell, a voltage-signal-generation circuit, a switch circuit, a detection circuit, and a controller. The variable-resistance memory cell includes a variable-resistance component and a transistor. The voltage-signal-generation circuit is coupled to the control terminal of the transistor. The switch circuit is coupled to the variable-resistance component and transistor. The detection circuit is coupled to a voltage source and the switch circuit. The controller is coupled to the voltage-signal-generation circuit, switch circuit, and detection circuit. When the controller performs a writing operation on the variable-resistance memory cell, the voltage-signal-generation circuit provides a voltage signal to the transistor, and the detection circuit continuously detects whether the variable-resistance component performs a resistance conversion. If the resistance conversion occurs, then the controller stops the writing operation.

公开(公告)号：US20170122892A1

公开(公告)日：2017-05-04

申请号：US14961906

申请日：2015-12-08

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/121 ,  G01N27/127

Abstract: A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

公开(公告)号：US20160118120A1

公开(公告)日：2016-04-28

申请号：US14749651

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Pei-Ling Tseng ,  Chia-Chen Kuo ,  Shyh-Shyuan Sheu ,  Meng-Fan Chang

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.

Abstract translation: 提供了一种电阻式存储器系统，其驱动电路及其电阻设定方法。 电阻式存储器系统包括存储器阵列，行选择电路，第一控制电路和第二控制电路。 存储器阵列具有多个电阻存储单元。 行选择电路用于激活电阻式存储单元。 第一控制电路和第二控制电路耦合到电阻存储器单元。 当每个电阻性存储器单元被设置时，第一控制电路和第二控制电路分别向每个电阻存储器单元提供一个设定电压和一个接地电压以形成一个设定电流，并且将该设定电流钳位在至少一个 的第一控制电路和第二控制电路。