公开(公告)号：US20200212297A1

公开(公告)日：2020-07-02

申请号：US16236705

申请日：2018-12-31

Applicant: Headway Technologies, Inc.

Inventor： Yi Yang ,  Vignesh Sundar ,  Dongna Shen ,  Sahil Patel ,  Ru-Ying Tong ,  Yu-Jen Wang

IPC: H01L43/12

Abstract: A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.

公开(公告)号：US20180358545A1

公开(公告)日：2018-12-13

申请号：US15619825

申请日：2017-06-12

Applicant: Headway Technologies, Inc.

Inventor： Vignesh Sundar ,  Yu-Jen Wang ,  Dongna Shen ,  Sahil Patel ,  Ru-Ying Tong

IPC: H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  H01L21/02 ,  G11C11/15 ,  G11C11/16

CPC classification number: H01L43/10 ,  C23C16/308 ,  C23C16/505 ,  G11C11/15 ,  G11C11/161 ,  H01L21/02126 ,  H01L21/02274 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

公开(公告)号：US20170256703A1

公开(公告)日：2017-09-07

申请号：US15599755

申请日：2017-05-19

Applicant: Headway Technologies, Inc.

Inventor： Jian Zhu ,  Guenole Jan ,  Yuan-Jen Lee ,  Huanlong Liu ,  Ru-Ying Tong ,  Jodi Mari Iwata ,  Vignesh Sundar ,  Luc Thomas ,  Yu-Jen Wang ,  Sahil Patel

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/16 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/303 ,  H01L43/08 ,  H01L43/10

Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

公开(公告)号：US11631802B2

公开(公告)日：2023-04-18

申请号：US16677053

申请日：2019-11-07

Applicant: Headway Technologies, Inc.

Inventor： Vignesh Sundar ,  Yi Yang ,  Dongna Shen ,  Zhongjian Teng ,  Jesmin Haq ,  Sahil Patel ,  Yu-Jen Wang ,  Tom Zhong

IPC: H01L43/00 ,  H01L41/47 ,  H01L41/047 ,  H01L41/332 ,  H01L41/06 ,  H01L41/053 ,  H01L41/20

Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

公开(公告)号：US11031548B2

公开(公告)日：2021-06-08

申请号：US16672981

申请日：2019-11-04

Applicant: Headway Technologies, Inc.

Inventor： Dongna Shen ,  Yi Yang ,  Sahil Patel ,  Vignesh Sundar ,  Yu-Jen Wang

IPC: H01L43/12 ,  H01L43/02

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A MTJ film stack is deposited on a bottom electrode on a substrate. The MTJ film stack is first ion beam etched (IBE) using a first angle and a first energy to form a MTJ device wherein conductive re-deposition forms on sidewalls of the MTJ device. Thereafter, the conductive re-deposition is oxidized. Thereafter, the MTJ device is second ion beam etched (IBE) at a second angle and a second energy to remove oxidized re-deposition.

公开(公告)号：US20210143322A1

公开(公告)日：2021-05-13

申请号：US16677053

申请日：2019-11-07

Applicant: Headway Technologies, Inc.

Inventor： Vignesh Sundar ,  Yi Yang ,  Dongna Shen ,  Zhongjian Teng ,  Jesmin Haq ,  Sahil Patel ,  Yu-Jen Wang ,  Tom Zhong

IPC: H01L41/47 ,  H01L41/047 ,  H01L41/20 ,  H01L41/06 ,  H01L41/053 ,  H01L41/332

Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

公开(公告)号：US20180331279A1

公开(公告)日：2018-11-15

申请号：US15595484

申请日：2017-05-15

Applicant: Headway Technologies, Inc.

Inventor： Dongna Shen ,  Yu-Jen Wang ,  Ru-Ying Tong ,  Vignesh Sundar ,  Sahil Patel

IPC: H01L43/12 ,  H01L21/306 ,  B82Y40/00 ,  B81C1/00 ,  H01L21/3065

CPC classification number: H01L43/12 ,  B81C1/00111 ,  B81C1/00523 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3065

Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.

公开(公告)号：US10115892B2

公开(公告)日：2018-10-30

申请号：US15599755

申请日：2017-05-19

Applicant: Headway Technologies, Inc.

Inventor： Jian Zhu ,  Guenole Jan ,  Yuan-Jen Lee ,  Huanlong Liu ,  Ru-Ying Tong ,  Jodi Mari Iwata ,  Vignesh Sundar ,  Luc Thomas ,  Yu-Jen Wang ,  Sahil Patel

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/16 ,  H01F10/30 ,  H01F10/32 ,  G11C11/16 ,  H01F41/30

Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 × to 30 × that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is Ta or TaN, for example. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded memory devices, or read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M may be B.