公开(公告)号：US11990461B2

公开(公告)日：2024-05-21

申请号：US17970237

申请日：2022-10-20

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US20240036278A1

公开(公告)日：2024-02-01

申请号：US17877041

申请日：2022-07-29

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Zuowei Shen ,  Yujeong Shim ,  Teckgyu Kang ,  Jaesik Lee ,  Georgios Konstadinidis ,  Sukalpa Biswas ,  Hong Liu ,  Biao He

IPC: G02B6/42 ,  H01L23/367 ,  H01L23/473 ,  H01L25/16

CPC classification number: G02B6/4268 ,  G02B6/4274 ,  G02B6/4257 ,  H01L23/3675 ,  H01L23/473 ,  H01L25/167

Abstract: The technology generally relates to high bandwidth memory (HBM) and optical connectivity stacking. Disclosed systems and methods herein allow for 3D-stacking of HBM dies that are interconnected with an optical interface in a manner that allows for compact, high-performance computing. An optical chiplet can be configured to be placed onto a stack of HBM dies, with a cooling die that is positioned between the HBM dies and the optical chiplet. The optical chiplet may be configured to connect the HBM optics module package to one or more other components of the package via to one or more optical fibers.

公开(公告)号：US20230343768A1

公开(公告)日：2023-10-26

申请号：US17992241

申请日：2022-11-22

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Zuowei Shen ,  Hong Liu ,  Yujeong Shim ,  Biao He ,  Jaesik Lee ,  Georgios Konstadinidis ,  Teckgyu Kang ,  Igor Arsovski ,  Sukalpa Biswas

IPC: H01L25/16

CPC classification number: H01L25/167

Abstract: The technology generally relates to disaggregating memory from an application specific integrated circuit (“ASIC”) package. For example, a high-bandwidth memory (“HBM”) optics module package may be connected to an ASIC package via one or more optical links. The HBM optics module package may include HBM dies(s), HBM chiplet(s) and an optical chiplet. The optical chiplet may be configured to connect the HBM optics module to one or more optical fibers that form an optical link with one or more other components of the ASIC package. By including an optical chiplet in the HBM optics module package, the HBM optics module package may be disaggregated from an ASIC package.

公开(公告)号：US20230335541A1

公开(公告)日：2023-10-19

申请号：US17719857

申请日：2022-04-13

Applicant: Google LLC

Inventor： Houle Gan ,  Richard Stuart Roy ,  Yujeong Shim ,  William F. Edwards, JR. ,  Chenhao Nan

IPC: H01L25/16 ,  H05K1/18 ,  H05K1/11

CPC classification number: H01L25/162 ,  H05K1/183 ,  H05K1/11 ,  H05K2201/10719 ,  H05K2201/10704 ,  H01L24/16

Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contact pads that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board.

公开(公告)号：US20240250082A1

公开(公告)日：2024-07-25

申请号：US18624411

申请日：2024-04-02

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US20230402430A1

公开(公告)日：2023-12-14

申请号：US18239368

申请日：2023-08-29

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11830855B2

公开(公告)日：2023-11-28

申请号：US17667104

申请日：2022-02-08

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20230335928A1

公开(公告)日：2023-10-19

申请号：US17722860

申请日：2022-04-18

Applicant: Google LLC

Inventor： William F. Edwards, JR. ,  Xu Zuo ,  Ryohei Urata ,  Melanie Beauchemin ,  Woon-Seong Kwon ,  Shinnosuke Yamamoto ,  Houle Gan ,  Yujeong Shim

IPC: H01R12/70 ,  H01R13/66 ,  H01R13/533

CPC classification number: H01R12/7064 ,  H01R13/533 ,  H01R13/6683

Abstract: An assembly includes a printed circuit board (“PCB”). An aperture extends through the PCB. The assembly also includes an array of pins and a processor package. The array of pins extends around a perimeter of the aperture, and the processor package extends over the aperture. The processor package is pressed against the array of pins by a compressive force couple.

公开(公告)号：US20230042856A1

公开(公告)日：2023-02-09

申请号：US17970237

申请日：2022-10-20

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US20210249384A1

公开(公告)日：2021-08-12

申请号：US16788994

申请日：2020-02-12

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.