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公开(公告)号：US10205116B2
公开(公告)日：2019-02-12
申请号：US15039639
申请日：2015-11-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Liang Sun
Abstract: An OLED array substrate and a method for manufacturing the same, an OLED packaging structure and a display device are provided by the present disclosure. The OLED array substrate includes thin film transistors, anodes, cathodes and organic light-emitting layers arranged between the anodes and the cathodes. The OLED array substrate further includes spacers configured to support the OLED array substrate and a packaging substrate so as to form a cell gap therebetween. Each cathode includes a first region which covers the corresponding first spacer and a second region beyond the first regions, and a thickness of the cathode at the first region is larger than a thickness of the cathode at the second region.
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公开(公告)号：US10036906B2
公开(公告)日：2018-07-31
申请号：US15322549
申请日：2016-04-15
Applicant: Boe Technology Group Co., Ltd.
Inventor： Zuqiang Wang , Guang Li , Liang Sun , Xiaoyong Lu
IPC: G02F1/13 , G02F1/1362 , G02F1/1333 , H01L27/32 , G01R31/28 , G02F1/1368
CPC classification number: G02F1/1309 , G01R31/2825 , G02F1/133345 , G02F1/136286 , G02F1/1368 , G02F2001/136254 , G02F2001/136295 , G09G3/006 , G09G3/3208 , G09G2300/0417 , H01L22/34 , H01L27/1214 , H01L27/3262 , H01L2227/323
Abstract: A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.
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公开(公告)号：US09768312B2
公开(公告)日：2017-09-19
申请号：US14913048
申请日：2015-07-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongwei Tian , Yanan Niu , Zuqiang Wang , Liang Sun
IPC: H01L29/786 , H01L21/77 , H01L21/02 , H01L21/225 , H01L21/30 , H01L21/306 , H01L27/12 , H01L29/10 , H01L29/66
CPC classification number: H01L29/78675 , H01L21/02532 , H01L21/02592 , H01L21/02675 , H01L21/2251 , H01L21/3003 , H01L21/30604 , H01L21/77 , H01L27/1222 , H01L27/127 , H01L27/1285 , H01L29/1033 , H01L29/66757 , H01L29/786 , H01L29/78696
Abstract: Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device. The manufacturing method of a thin film transistor includes a step of forming an active layer, and the step of forming an active layer includes: forming a first poly-silicon layer and a second poly-silicon layer on the first poly-silicon layer separately, and adding dopant ions into the second poly-silicon layer and an upper surface layer of the first poly-silicon layer. By using the manufacturing method of a thin film transistor, defect states and unstable factors of interface in the thin film transistor can be reduced, thereby improving stability of the LTPS thin film transistor and obtaining an array substrate and a display device having more stable performance.
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公开(公告)号：US09673421B2
公开(公告)日：2017-06-06
申请号：US14436014
申请日：2014-08-07
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Liang Sun
CPC classification number: H01L51/5265 , H01L27/3211 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L51/5209 , H01L51/5218 , H01L51/5221 , H01L51/5225 , H01L51/56 , H01L2227/323 , H01L2251/301 , H01L2251/308 , H01L2251/5315
Abstract: An organic light-emitting diode (OLED) display and a manufacturing method thereof are provided. The OLED display includes a plurality of sub-pixel units each including a first region and a second region. The first region includes a first electrode, a first organic material functional layer and a second electrode disposed in order on a base substrate. The second region includes a third electrode, a second organic material functional layer and a fourth electrode disposed in order on the base substrate. The first electrode and the third electrode each include an opaque metal layer, and the second electrode and the fourth electrode are translucent metal electrodes. The first electrode, the first organic material functional layer and the second electrode constitute a first micro-cavity, the third electrode, the second organic material functional layer and the fourth electrode constitute a second micro-cavity, and the first micro-cavity and the second micro-cavity have different micro-cavity effects.
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公开(公告)号：US20170039944A1
公开(公告)日：2017-02-09
申请号：US14908835
申请日：2015-08-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhanjie Ma , Liang Sun
IPC: G09G3/3258 , G09G3/3291 , G09G3/325 , G09G3/3266
CPC classification number: G09G3/3258 , G09G3/3233 , G09G3/325 , G09G3/3266 , G09G3/3291 , G09G2300/0809 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0262 , G09G2320/0233 , G09G2320/045 , G09G2320/0646
Abstract: The present invention provides a pixel circuit, a driving method thereof and a display device which are related to the field of display technology. The pixel circuit comprises a reset module, a compensation module, an energy storage module, a drive module, a drive control module, a power supply module and a light emitting module, the input voltage of the third power supply signal terminal is larger than the difference between the input voltage of the data signal terminal and the threshold voltage of the drive module, and is less than the input voltage of the second power supply signal terminal. The present invention is capable of discharging the driving transistor to a potential Vth within a short period, ensuring the driving transistor to be discharged completely in a short time.
Abstract translation: 本发明提供了与显示技术领域相关的像素电路，其驱动方法和显示装置。 像素电路包括复位模块，补偿模块，能量存储模块，驱动模块，驱动控制模块，电源模块和发光模块，第三电源信号端子的输入电压大于 数据信号端子的输入电压与驱动模块的阈值电压之差，小于第二电源信号端子的输入电压。 本发明能够在短时间内将驱动晶体管放电至电位Vth，从而确保驱动晶体管在短时间内完全放电。
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Patent Agency Ranking
16.发明申请OLED PANEL,L METHOD FOR FABRICATING THE SAME, SCREEN PRINTING PLATE, DISPLAY DEVICE 有权OLED面板，L制造它们的方法，屏幕印刷板，显示装置公开(公告)号：US20160329528A1
公开(公告)日：2016-11-10
申请号：US14784640
申请日：2015-03-06
Applicant: Boe Technology Group Co., Ltd.
Inventor： Liang Sun
CPC classification number: H01L51/56 , B41F15/02 , B41F15/36 , H01L51/524
Abstract: The present invention provides an OLED panel and a method for fabricating the same, a screen printing plate, and a display device. The method comprises: forming an OLED mother board, wherein supporting adhesive is formed between an upper base plate and a lower base plate of the OLED mother board, and said supporting adhesive is located below a cutting line; and cutting said OLED mother board along said cutting line to obtain OLED panels. In the fabricating method of the present invention, when the OLED mother board is cut by a cutter wheel, the upper and lower base plate of the OLED mother board is subject to small deformation due to support of the supporting adhesive. As a result, travelling accuracy of the cutter wheel is improved, the distance between the cutting line and packaging adhesive is greatly reduced, and the frame width of the fabricated OLED panel is far less than that of an OLED panel fabricated by a conventional method.
Abstract translation: 本发明提供一种OLED面板及其制造方法，丝网印刷版和显示装置。 该方法包括：形成OLED母板，其中在OLED母板的上基板和下基板之间形成支撑粘合剂，并且所述支撑粘合剂位于切割线下方; 并沿所述切割线切割所述OLED母板以获得OLED面板。 在本发明的制造方法中，当通过切割轮切割OLED母板时，由于支撑粘合剂的支撑，OLED母板的上基板和下基板受到小的变形。 结果，切割轮的移动精度提高，切割线和包装粘合剂之间的距离大大降低，并且所制造的OLED面板的框架宽度远远小于通过常规方法制造的OLED面板的宽度。
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公开(公告)号：US20140160418A1
公开(公告)日：2014-06-12
申请号：US14103274
申请日：2013-12-11
Inventor： Xiaming ZHU , Liang Sun , Jianfeng Yuan , Seung Moo Rim , Xibin Shao
IPC: G02F1/1343
CPC classification number: G02F1/1333 , G02F1/1309 , G02F1/1345 , G02F1/136204 , G02F1/136286 , G02F2001/134372 , G02F2201/121 , G02F2202/22
Abstract: The present invention relates to an array substrate for an LCD display and manufacturing method. The array substrate comprise a transparent substrate, gate lines and data lines disposed on the transparent substrate, a transparent conducting bar and a gate short-circuit bar. The transparent conducting bar is disposed below the gate short-circuit bar with the gate short-circuit bar and data lines arranged in the same layer. The present invention avoids the problem of burning the gate short-circuit bar due to the occurrence of static discharge and electrical defects in the array substrate are detectable and repairable in the array test process, improving the product rate of the LCD array substrate.
Abstract translation: 本发明涉及一种液晶显示器用阵列基板及其制造方法。 阵列基板包括透明基板，设置在透明基板上的栅极线和数据线，透明导电条和栅极短路条。 透明导电棒设置在栅极短路棒的下方，栅极短路棒和数据线布置在同一层中。 本发明避免了由于静电放电的发生而导致的栅极短路棒烧毁的问题，并且阵列基板中的电气缺陷在阵列测试过程中是可检测的和可修复的，从而提高了LCD阵列基板的产品率。
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公开(公告)号：US20140054282A1
公开(公告)日：2014-02-27
申请号：US13984387
申请日：2013-03-19
Inventor： Shoukun Wang , Liang Sun
IPC: H05B1/02
CPC classification number: H05B1/0288 , H01L21/67103 , H01L21/67109 , H01L21/68742
Abstract: According to embodiments of present invention, a baseplate supporting pin is provided, which comprises: a pin body; a heating device embedded into the pin body; and a first control unit electrically connected to the heating device for controlling the heating device. Furthermore, according to embodiments of present invention, a baseplate supporting device is provided, which comprises: a baseplate support member; and a baseplate supporting pin, provided to ascend or descend through an opening formed in the baseplate supporting plate so as to support the baseplate thereon or place the baseplate on the baseplate support member, wherein the baseplate supporting pin comprises: a pin body; a heating device built in the pin body; and a first control unit electrically connected to the heating device for controlling the heating device. The baseplate supporting pin and the baseplate supporting device facilitate eliminating adverse effect caused by uneven heating of the baseplate.
Abstract translation: 根据本发明的实施例，提供了一种底板支撑销，其包括：销体; 嵌入销体的加热装置; 以及电连接到加热装置用于控制加热装置的第一控制单元。 此外，根据本发明的实施例，提供了一种基板支撑装置，其包括：基板支撑构件; 以及底板支撑销，其设置成通过形成在基板支撑板中的开口上升或下降，以便在其上支撑基板或将基板放置在基板支撑构件上，其中底板支撑销包括：销体; 内置在销体内的加热装置; 以及电连接到加热装置用于控制加热装置的第一控制单元。 底板支撑销和底板支撑装置有助于消除由于底板不均匀加热引起的不利影响。
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公开(公告)号：US12237449B2
公开(公告)日：2025-02-25
申请号：US18561741
申请日：2021-05-27
Inventor： Enkai Dong , Liang Sun , Jiacheng Qi
IPC: H01L33/54 , G02F1/1335 , G02F1/13357
Abstract: A backlight module comprises a driving backplate, which comprises multiple pads; multiple light-emitting diodes, which are electrically connected to the pads; and multiple transparent protection structures, which are located on the sides of the multiple light-emitting diodes that are away from the driving backplate, wherein the transparent protection structures cover the light-emitting diodes, there is a first distance between the center of the orthographic projection of each transparent protection structure on the driving backplate and the center of the orthographic projection of each light-emitting diode on the driving backplate; and the length of the orthographic projection of each light-emitting diode on the driving backplate is a second distance, the width of the orthographic projection of each light-emitting diode on the driving backplate is a third distance, the ratio of the first distance to the second distance is less than or equal to 1:2-1:10.
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公开(公告)号：US10090831B2
公开(公告)日：2018-10-02
申请号：US15122389
申请日：2015-04-09
Inventor： Jun Wang , Xinxin Jin , Liang Sun , Yuebai Han , Guoqing Zhang
IPC: G09G3/3233 , H03K17/16
Abstract: The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs
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