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公开(公告)号:US20180198091A1
公开(公告)日:2018-07-12
申请号:US15864911
申请日:2018-01-08
Applicant: Applied Materials, Inc.
Inventor: Jrjyan Jerry CHEN , Soo Young CHOI , Xiangxin RUI
CPC classification number: H01L51/5253 , C23C16/042 , C23C16/308 , C23C16/345 , C23C16/402 , C23C16/403 , C23C16/405 , C23C16/407 , C23C16/50 , C23C16/505 , C23C16/56 , H01L21/67167 , H01L21/67742 , H01L21/681 , H01L51/56
Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure with desired profile control of the TFE structure. In one example, a method for forming a thin film encapsulation structure over an OLED structure includes forming a thin film encapsulation structure over an OLED structure disposed on a substrate, and performing a plasma treatment process to the thin film encapsulation structure by supplying a treatment gas mixture including a halogen containing gas to the thin film encapsulation structure.
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12.
公开(公告)号:US20240347551A1
公开(公告)日:2024-10-17
申请号:US18750424
申请日:2024-06-21
Applicant: Applied Materials, Inc.
Inventor: Xiangxin RUI , Lai ZHAO , Jrjyan Jerry CHEN , Soo Young CHOI , Yujia ZHAI
IPC: H01L27/12 , H01L29/49 , H01L29/786
CPC classification number: H01L27/1255 , H01L27/1222 , H01L27/1237 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L28/55 , H01L29/4908 , H01L29/78675
Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.
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公开(公告)号:US20200017971A1
公开(公告)日:2020-01-16
申请号:US16032854
申请日:2018-07-11
Applicant: Applied Materials, Inc.
Inventor: Chien-Teh KAO , Jeffrey A. KHO , Xiangxin RUI , Jianhua ZHOU , Shinichi KURITA , Shouqian SHAO , Guangwei SUN
IPC: C23C16/455 , C23C16/44
Abstract: Embodiments described herein provide a chamber having a gas flow inlet guide to uniformly deliver process gas and a gas flow outlet guide to effectively purge process gasses and reduce purge time. The chamber includes a chamber body having a process gas inlet and a process gas outlet, a lid assembly, a process gas inlet and a process gas outlet configured to be in fluid communication with a processing region in the chamber, a gas flow inlet guide disposed in the process gas inlet, and a gas flow outlet guide disposed in the process gas outlet. The gas flow inlet guide includes a flow modulator and at least two first inlet guide channels having first inlet guide channel areas that are different. The gas flow outlet guide includes at least two first outlet guide channels having first outlet guide channel areas that are different.
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公开(公告)号:US20180155835A1
公开(公告)日:2018-06-07
申请号:US15829667
申请日:2017-12-01
Applicant: Applied Materials, Inc.
Inventor: Shinichi KURITA , Srikanth V. RACHERLA , Suhas BHOSKI , Xiangxin RUI
IPC: C23C16/455 , C23C16/458 , C23C16/44 , C23C16/04
CPC classification number: C23C16/45544 , C23C16/042 , C23C16/4401 , C23C16/4412 , C23C16/45529 , C23C16/45542 , C23C16/458 , C23C16/54
Abstract: The present disclosure relates to methods and apparatus for a thin film encapsulation (TFE). In one embodiment a process kit for use in an atomic layer deposition (ALD) chamber is disclosed and includes a dielectric window, a sealing frame, and a mask frame connected with the sealing frame, wherein the mask frame has a gas inlet channel and a gas outlet channel formed therein on opposing sides thereof.
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公开(公告)号:US20180114946A1
公开(公告)日:2018-04-26
申请号:US15843295
申请日:2017-12-15
Applicant: Applied Materials, Inc.
Inventor: Jrjyan Jerry CHEN , Xiangxin RUI , Soo Young CHOI
IPC: H01L51/52 , H01L21/67 , H01L21/687 , H01L21/677
CPC classification number: H01L51/5256 , H01L21/67167 , H01L21/6719 , H01L21/67207 , H01L21/67742 , H01L21/68742 , H01L21/68785 , H01L21/68792
Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure. The TFE structure includes at least one dielectric layer and at least two barrier layers, and the TFE structure is formed over the OLED structure. The at least one dielectric layer is deposited by atomic layer deposition (ALD). Having the at least one dielectric layer formed by ALD in the TFE structure improves the barrier performance of the TFE structure.
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16.
公开(公告)号:US20180026055A1
公开(公告)日:2018-01-25
申请号:US15617888
申请日:2017-06-08
Applicant: Applied Materials, Inc.
Inventor: Xiangxin RUI , Lai ZHAO , Jrjyan Jerry CHEN , Soo Young CHOI , Yujia ZHAI
IPC: H01L27/12 , H01L29/786 , H01L49/02 , H01L29/49
CPC classification number: H01L27/1255 , H01L27/1222 , H01L27/1237 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L28/55 , H01L29/4908 , H01L29/78675
Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer comprising metal, and a gate electrode formed above or below the gate insulating layer
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17.
公开(公告)号:US20220013547A1
公开(公告)日:2022-01-13
申请号:US17487086
申请日:2021-09-28
Applicant: Applied Materials, Inc.
Inventor: Xiangxin RUI , Lai ZHAO , Jrjyan Jerry CHEN , Soo Young CHOI , Yujia ZHAI
IPC: H01L27/12 , H01L49/02 , H01L29/49 , H01L29/786
Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.
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公开(公告)号:US20210288084A1
公开(公告)日:2021-09-16
申请号:US17332766
申请日:2021-05-27
Applicant: Applied Materials, Inc.
Inventor: Xiangxin RUI , Soo Young CHOI , Shinichi KURITA , Yujia ZHAI , Lai ZHAO
IPC: H01L27/12 , H01L49/02 , H01L29/49 , H01L29/786 , H01L21/02 , H01J37/32 , C23C16/40 , C23C16/50 , C23C16/455 , C23C16/52 , C23C16/56 , H01L21/687 , H01L21/67
Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.
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公开(公告)号:US20200258918A1
公开(公告)日:2020-08-13
申请号:US15773640
申请日:2017-07-11
Applicant: Applied Materials, Inc.
Inventor: Xiangxin RUI , Lai ZHAO , Jrjyan Jerry CHEN , Soo Young CHOI , Yujia ZHAI
IPC: H01L27/12 , H01L29/24 , H01L29/66 , H01L29/786
Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.
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20.
公开(公告)号:US20180350571A1
公开(公告)日:2018-12-06
申请号:US15613862
申请日:2017-06-05
Applicant: Applied Materials, Inc.
Inventor: Yujia ZHAI , Wenqing DAI , Lai ZHAO , Xiangxin RUI , Dong Kil YIM , Tae Kyung WON , Soo Young CHOI
IPC: H01J37/32 , C22F1/18 , C23C16/455 , C23C16/44
Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a substrate-processing chamber. In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual ZrO2 containing film formed on one or more interior surfaces of the processing chamber. The reactive species is formed from BCl3 and the one or more interior surfaces includes at least one exposed Al2O3 surface The method further comprises reacting the residual ZrO2 containing film with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber, wherein a removal rate of the residual ZrO2 containing film is greater than a removal rate of Al2O3.
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