公开(公告)号：US20250094174A1

公开(公告)日：2025-03-20

申请号：US18783937

申请日：2024-07-25

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US11921640B2

公开(公告)日：2024-03-05

申请号：US17727031

申请日：2022-04-22

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephan G. Meier

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F9/3877 ,  G06F12/0292 ,  G06F12/0833 ,  G06F12/0862 ,  G06F12/126 ,  G06F2212/1021

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

公开(公告)号：US11886354B1

公开(公告)日：2024-01-30

申请号：US17664379

申请日：2022-05-20

Applicant: Apple Inc.

Inventor： Anwar Q. Rohillah ,  Tyler J. Huberty

IPC: G06F12/128 ,  G06F1/3225 ,  G06F12/0891

CPC classification number: G06F12/128 ,  G06F1/3225 ,  G06F12/0891 ,  G06F2212/1021

Abstract: Techniques are disclosed relating to cache thrash detection. In some embodiments, cache controller circuitry is configured to monitor and track performance metrics across multiple levels of a cache hierarchy, detect cache thrashing based on one or more performance metrics, and modify a cache insertion policy to mitigate cache thrashing. Disclosed techniques may advantageously detect and reduce or avoid cache thrashing, which may increase processor performance, decrease power consumption for a given workload, or both, relative to traditional techniques.

公开(公告)号：US20230092898A1

公开(公告)日：2023-03-23

申请号：US17643765

申请日：2021-12-10

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38 ,  G06F9/34 ,  G06F12/10

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US20230066236A1

公开(公告)日：2023-03-02

申请号：US17727020

申请日：2022-04-22

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephan G. Meier

IPC: G06F12/0891 ,  G06F12/0831 ,  G06F12/126 ,  G06F12/02

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

公开(公告)号：US10776521B2

公开(公告)日：2020-09-15

申请号：US15679031

申请日：2017-08-16

Applicant: Apple Inc.

Inventor： Jeremie S. Kim ,  Minesh H. Patel ,  Stephan G. Meier ,  Tyler J. Huberty ,  Onur Mutlu

IPC: G06F21/71 ,  H04L9/32 ,  G06F21/44 ,  G06F21/73 ,  G06F21/72 ,  H04L29/06

Abstract: Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

公开(公告)号：US09904624B1

公开(公告)日：2018-02-27

申请号：US15093173

申请日：2016-04-07

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Stephan G. Meier ,  Khubaib Khubaib

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/602

Abstract: In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.

公开(公告)号：US12050918B2

公开(公告)日：2024-07-30

申请号：US18361244

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3877

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US20240095037A1

公开(公告)日：2024-03-21

申请号：US18361244

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3877

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US11768690B2

公开(公告)日：2023-09-26

申请号：US17532072

申请日：2021-11-22

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Brian P. Lilly ,  James Vash ,  Jason M. Kassoff ,  Krishna C. Potnuru ,  Rajdeep L. Bhuyar ,  Ran A. Chachick ,  Tyler J. Huberty ,  Derek R. Kumar

IPC: G06F9/38 ,  G06F11/30 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/3877 ,  G06F9/3009 ,  G06F9/3836 ,  G06F9/3863 ,  G06F9/3881 ,  G06F9/4887 ,  G06F11/3024 ,  G06F9/3879

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.