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    Insertion/promotion vectors to update replacement data in caches based on criticality
    3.
    发明授权
    Insertion/promotion vectors to update replacement data in caches based on criticality 有权

    公开(公告)号：US12222875B1

    公开(公告)日：2025-02-11

    申请号：US18361169

    申请日：2023-07-28

    Applicant: Apple Inc.

    Inventor： Tyler J. Huberty ,  Henry A. Pellerin ,  Daniel A. Jimenez

    IPC: G06F12/123

    Abstract: A cache memory supports a plurality of insertion/promotion vectors (IPVs) and a replacement control circuit configured to update replacement data for the cache memory based on the plurality of IPVs. In one embodiment, the IPV is selected for a given request based a criticality status of a cache line accessed by the given request. For example, cache lines deemed important or critical for performance reasons may be replaced less frequently via a first IPV, while non-critical cache lines are replaced more frequently via a second IPV.

    Secondary Prefetch Circuit that Reports Coverage to a Primary Prefetch Circuit to Limit Prefetching by Primary Prefetch Circuit
    4.
    发明申请
    Secondary Prefetch Circuit that Reports Coverage to a Primary Prefetch Circuit to Limit Prefetching by Primary Prefetch Circuit 有权

    公开(公告)号：US20210303471A1

    公开(公告)日：2021-09-30

    申请号：US16832893

    申请日：2020-03-27

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta

    IPC: G06F12/0862

    Abstract: In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

    Unified prefetch circuit for multi-level caches
    5.
    发明授权
    Unified prefetch circuit for multi-level caches 有权

    公开(公告)号：US10180905B1

    公开(公告)日：2019-01-15

    申请号：US15093213

    申请日：2016-04-07

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Gerard R. Williams, III ,  Pradeep Kanapathipillai

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0811

    Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

    SECURITY TECHNIQUES BASED ON MEMORY TIMING CHARACTERISTICS
    6.
    发明申请
    SECURITY TECHNIQUES BASED ON MEMORY TIMING CHARACTERISTICS 审中-公开

    公开(公告)号：US20180307862A1

    公开(公告)日：2018-10-25

    申请号：US15679031

    申请日：2017-08-16

    Applicant: Apple Inc.

    Inventor： Jeremie S. Kim ,  Minesh H. Patel ,  Stephan G. Meier ,  Tyler J. Huberty ,  Onur Mutlu

    IPC: G06F21/71 ,  H04L9/32 ,  G06F21/44

    Abstract: Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

    Prefetch circuit with global quality factor to reduce aggressiveness in low power modes
    10.
    发明授权
    Prefetch circuit with global quality factor to reduce aggressiveness in low power modes 有权

    公开(公告)号：US10331567B1

    公开(公告)日：2019-06-25

    申请号：US15435910

    申请日：2017-02-17

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta ,  Francesco Spadini ,  Gideon Levinsky

    IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/12

    Abstract: A prefetch circuit may include a memory, each entry of which may store an address and other prefetch data used to generate prefetch requests. For each entry, there may be at least one “quality factor” (QF) that may control prefetch request generation for that entry. A global quality factor (GQF) may control generation of prefetch requests across the plurality of entries. The prefetch circuit may include one or more additional prefetch mechanisms. For example, a stride-based prefetch circuit may be included that may generate prefetch requests for strided access patterns having strides larger than a certain stride size. Another example is a spatial memory streaming (SMS)-based mechanism in which prefetch data from multiple evictions from the memory in the prefetch circuit is captured and used for SMS prefetching based on how well the prefetch data appears to match a spatial memory streaming pattern.

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