公开(公告)号：US12222875B1

公开(公告)日：2025-02-11

申请号：US18361169

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Henry A. Pellerin ,  Daniel A. Jimenez

IPC: G06F12/123

Abstract: A cache memory supports a plurality of insertion/promotion vectors (IPVs) and a replacement control circuit configured to update replacement data for the cache memory based on the plurality of IPVs. In one embodiment, the IPV is selected for a given request based a criticality status of a cache line accessed by the given request. For example, cache lines deemed important or critical for performance reasons may be replaced less frequently via a first IPV, while non-critical cache lines are replaced more frequently via a second IPV.