知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.013 seconds)

    Variable hit latency cache
    1.
    发明授权
    Variable hit latency cache 有权

    公开(公告)号：US11893241B1

    公开(公告)日：2024-02-06

    申请号：US17823695

    申请日：2022-08-31

    Applicant: Apple Inc.

    Inventor： Brian P. Lilly ,  Sandeep Gupta ,  Chandan Shantharaj ,  Krishna C. Potnuru ,  Sahil Kapoor

    IPC: G06F3/06 ,  G06F12/0877

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0877 ,  G06F2212/60

    Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.

    Debug Trace of Cache Memory Requests
    3.
    发明公开
    Debug Trace of Cache Memory Requests 审中-公开

    公开(公告)号：US20230418724A1

    公开(公告)日：2023-12-28

    申请号：US18344170

    申请日：2023-06-29

    Applicant: Apple Inc.

    Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

    IPC: G06F11/34 ,  G06F11/30 ,  G06F12/02

    CPC classification number: G06F11/348 ,  G06F11/3037 ,  G06F12/0223 ,  G06F2212/1008

    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

    Request Ordering in a Cache
    4.
    发明公开
    Request Ordering in a Cache 审中-公开

    公开(公告)号：US20230359557A1

    公开(公告)日：2023-11-09

    申请号：US18353830

    申请日：2023-07-17

    Applicant: Apple Inc.

    Inventor： Sandeep Gupta ,  Brian P. Lilly ,  Krishna C. Potnuru

    IPC: G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/60

    Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

    Debug trace of cache memory requests
    5.
    发明授权
    Debug trace of cache memory requests 有权

    公开(公告)号：US11740993B2

    公开(公告)日：2023-08-29

    申请号：US17538939

    申请日：2021-11-30

    Applicant: Apple Inc.

    Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

    IPC: G06F12/00 ,  G06F11/34 ,  G06F11/30 ,  G06F12/02

    CPC classification number: G06F11/348 ,  G06F11/3037 ,  G06F12/0223 ,  G06F2212/1008

    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

    Debug Trace of Cache Memory Requests
    7.
    发明申请
    Debug Trace of Cache Memory Requests 有权

    公开(公告)号：US20230061419A1

    公开(公告)日：2023-03-02

    申请号：US17538939

    申请日：2021-11-30

    Applicant: Apple Inc.

    Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

    IPC: G06F11/34 ,  G06F12/02 ,  G06F11/30

    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

Patent Agency Ranking