公开(公告)号：US20240168887A1

公开(公告)日：2024-05-23

申请号：US18422584

申请日：2024-01-25

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephen G. Meier

IPC: G06F12/0891 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F9/3877 ,  G06F12/0292 ,  G06F12/0833 ,  G06F12/0862 ,  G06F12/126 ,  G06F2212/1021

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

公开(公告)号：US12235769B2

公开(公告)日：2025-02-25

申请号：US18422584

申请日：2024-01-25

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephen G. Meier

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/126

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

公开(公告)号：US20250094174A1

公开(公告)日：2025-03-20

申请号：US18783937

申请日：2024-07-25

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US20230092898A1

公开(公告)日：2023-03-23

申请号：US17643765

申请日：2021-12-10

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38 ,  G06F9/34 ,  G06F12/10

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US12050918B2

公开(公告)日：2024-07-30

申请号：US18361244

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3877

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US20240095037A1

公开(公告)日：2024-03-21

申请号：US18361244

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3877

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US11755333B2

公开(公告)日：2023-09-12

申请号：US17643765

申请日：2021-12-10

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3877

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.