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公开(公告)号：US20240377453A1
公开(公告)日：2024-11-14
申请号：US18666452
申请日：2024-05-16
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US11552190B2
公开(公告)日：2023-01-10
申请号：US16952500
申请日：2020-11-19
Inventor： Edward John Coyne , Alan Brannick , John P. Meskell
Abstract: A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.
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13.发明申请公开(公告)号：US20210098576A1
公开(公告)日：2021-04-01
申请号：US16590096
申请日：2019-10-01
Inventor： Edward John Coyne , Alan Brannick , Shane Tooher , Breandán Pol Og Ó hAnnaidh , Catriona Marie O'Sullivan , Shane Patrick Geary
IPC: H01L29/08 , H01L29/732 , H01L29/167 , H01L29/66 , H01L21/02 , H01L29/10 , H01L21/265
Abstract: A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.
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14.发明申请公开(公告)号：US20210098574A1
公开(公告)日：2021-04-01
申请号：US16590106
申请日：2019-10-01
Inventor： Edward John Coyne , Alan Brannick , Shane Tooher , Breandán Pol Og Ó hAnnaidh , Catriona Marie O'Sullivan , Shane Patrick Geary
IPC: H01L29/08 , H01L29/732 , H01L29/66 , H01L27/082 , H01L21/8228
Abstract: A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.
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15.发明申请公开(公告)号：US20250030237A1
公开(公告)日：2025-01-23
申请号：US18679379
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Stephen Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface and a plurality of pairs of conductive layers over the horizontal main surface. Different ones of the pairs are separated by different vertical distances such that each pair serves as an arcing electrode pair and different ones of the arcing electrode pairs are configured to arc discharge at different voltages.
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Patent Agency Ranking
公开(公告)号：US20240405519A1
公开(公告)日：2024-12-05
申请号：US18679364
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, a first conductive layer and a second conductive layer each extending over the substrate and substantially parallel to the horizontal main surface while being separated in a vertical direction crossing the horizontal main surface. One of the first and second conductive layers is electrically connected to a first voltage node and the other of the first and second conductive layers is electrically connected to a second voltage node. The first and second conductive layers serve as one or more arcing electrode pairs and have overlapping portions configured to generate one or more arc discharges extending generally in the vertical direction in response to an EOS voltage signal received between the first and second voltage nodes.
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17.发明公开公开(公告)号：US20230375600A1
公开(公告)日：2023-11-23
申请号：US18317806
申请日：2023-05-15
Inventor： David J. Clarke , Stephen Denis Heffernan , Nijun Wei , Alan J. O'Donnell , Patrick Martin McGuinness , Shaun Bradley , Edward John Coyne , David Aherne , David M. Boland
IPC: G01R19/165 , G01R31/00 , G01R31/28 , H02H9/04 , H01L27/02 , H01L23/60 , H01L23/62 , H01L23/525 , H02H9/00
CPC classification number: G01R19/16504 , G01R31/002 , G01R31/2832 , G01R31/2856 , H02H9/042 , H01L27/0288 , H01L23/60 , H01L23/62 , H01L23/5256 , H02H9/00
Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes;
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公开(公告)号：US11686763B2
公开(公告)日：2023-06-27
申请号：US17652857
申请日：2022-02-28
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
CPC classification number: G01R31/2879 , G01N27/041 , G01R31/2874
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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19.发明申请公开(公告)号：US20240405518A1
公开(公告)日：2024-12-05
申请号：US18679352
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
IPC: H01T4/10
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap device includes first and second conductive layers formed over a substrate, where the first and second conductive layers are electrically connected to first and second voltage nodes, respectively. The first conductive layer includes a plurality of arcing tips configured to form arcing electrode pairs with the second conductive layer to form an arc discharge in response to an EOS voltage between the first and second voltage nodes. The spark gap device further includes a series ballast resistor electrically connected between the arcing tips and the first voltage node, where the ballast resistor in formed in a metallization layer over the substrate and a resistance of the series ballast resistor is substantially higher than a resistance of the second conductive layer.
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公开(公告)号：US12055569B2
公开(公告)日：2024-08-06
申请号：US18317806
申请日：2023-05-15
Inventor： David J. Clarke , Stephen Denis Heffernan , Nijun Wei , Alan J. O'Donnell , Patrick Martin McGuinness , Shaun Bradley , Edward John Coyne , David Aherne , David M. Boland
IPC: G01R19/165 , G01R31/00 , G01R31/28 , H01L23/525 , H01L23/60 , H01L23/62 , H01L27/02 , H02H9/00 , H02H9/04
CPC classification number: G01R19/16504 , G01R31/002 , G01R31/2832 , G01R31/2856 , H01L23/5256 , H01L23/60 , H01L23/62 , H01L27/0288 , H02H9/00 , H02H9/042
Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.
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