公开(公告)号：US20090102038A1

公开(公告)日：2009-04-23

申请号：US12251624

申请日：2008-10-15

申请人： SIMON J.S. MCELREA ,  Marc E. Robinson ,  Lawrence Douglas Andrews, JR. ,  Terrence Caskey ,  Scott McGrath ,  Yong Du ,  Al Vindasius

发明人： SIMON J.S. MCELREA ,  Marc E. Robinson ,  Lawrence Douglas Andrews, JR. ,  Terrence Caskey ,  Scott McGrath ,  Yong Du ,  Al Vindasius

IPC分类号： H01L23/488 ,  H01L21/02

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06572

摘要： A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level.

摘要翻译： 准备用于堆叠在芯片级堆叠管芯组件中的管芯，其具有从管芯边缘向内的区域中的互连位置和在至少一个管芯边缘附近的互连焊盘。 可以通过组件中的第一管芯和支撑件上的电路之间的连接来进行堆叠管芯组件的二次互连; 并且堆叠中的管芯之间的互连可以通过z-互连与在支撑件的管芯附接侧中的接合焊盘附近或在一个或多个管芯边缘处的连接来进行。 用于制备模具的方法包括在晶片级或模具阵列级进行到高级阶段的工艺。

公开(公告)号：US06271598B1

公开(公告)日：2001-08-07

申请号：US08918500

申请日：1997-08-22

申请人： Alfons Vindasius ,  Marc E. Robinson ,  William R. Scharrenberg

发明人： Alfons Vindasius ,  Marc E. Robinson ,  William R. Scharrenberg

IPC分类号： H01L2348

CPC分类号： H01L24/81 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： A flip chip on chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, the present invention provides a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip. In still another preferred embodiment, the present invention provides a flip chip assembly including a semiconductor wafer having a plurality of first flip-chips formed thereon; a plurality of second flip chips, each one of the second flip chips directly connected to a respective one of the plurality of first flip-chips; and electrically conductive epoxy means disposed between the respective first flip-chip and second flip-chip connections to form an electrical connection between the respective first flip-chip and second flip chip connections. The present invention provides several very desirable features, including the ability to: (1) bond one die to another die in a flip chip fashion; (2) the ability to add a third die on top of the two flip chip die arrangement and wire bond that combination of three dies with two sets of wire bonds; and (3) the ability to further enhance the improved flip chip arrangement by combining a flip chip process (DCP) with a vertical integration process (VIP) to allow for the stacking of a plurality of die (e.g., N die). The flip chip on chip process according to the present invention provides for higher die density in the same board area and a reduction in the number of wires bonds that are required (therefore enhancing the reliability).

公开(公告)号：US08357999B2

公开(公告)日：2013-01-22

申请号：US11744142

申请日：2007-05-03

申请人： Marc E. Robinson ,  Alfons Vindasius ,  Donald Almen ,  Larry Jacobsen

发明人： Marc E. Robinson ,  Alfons Vindasius ,  Donald Almen ,  Larry Jacobsen

IPC分类号： H01L23/522

CPC分类号： H01L25/00 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的周边边缘处水平地插入并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US08704379B2

公开(公告)日：2014-04-22

申请号：US12199080

申请日：2008-08-27

申请人： Scott Jay Crane ,  Simon J. S. McElrea ,  Scott McGrath ,  Weiping Pan ,  DeAnn Eileen Melcher ,  Marc E. Robinson

发明人： Scott Jay Crane ,  Simon J. S. McElrea ,  Scott McGrath ,  Weiping Pan ,  DeAnn Eileen Melcher ,  Marc E. Robinson

IPC分类号： H01L23/48

CPC分类号： H01L24/83 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/27452 ,  H01L2224/29005 ,  H01L2224/29006 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

摘要： A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a conformal coating between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on either or both a die attach area of a surface of the die, or a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

摘要翻译： 半导体管芯上的保形涂层提供了管芯和支撑件之间的粘附。 不需要额外的粘合剂将模具固定在支撑件上。 共形涂层在组装期间保护模具，并且用于使模具与模具可接触的导电部件电绝缘。 保形涂层可以是有机聚合物，例如聚对二甲苯。 此外，将模具粘附到可任选地是另一个模具的支撑件上的方法包括在模具和支撑件之间提供共形涂层，以及加热模具和支撑件之间的涂层。 保形涂层可以设置在模具表面的芯片附接区域或支撑体表面的模具安装区域中的任一个或两者上; 并且可以在将模具放置在支撑件上之后提供保形涂层。

公开(公告)号：US07535109B2

公开(公告)日：2009-05-19

申请号：US11744153

申请日：2007-05-03

申请人： Marc E. Robinson ,  Alfons Vindasius ,  Donald Almen ,  Larry Jacobsen

发明人： Marc E. Robinson ,  Alfons Vindasius ,  Donald Almen ,  Larry Jacobsen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2924/09701 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需电连接焊盘上方的绝缘层中形成开口，并且管芯或多个管芯段 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的周边边缘处水平地插入并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US20090065916A1

公开(公告)日：2009-03-12

申请号：US12199080

申请日：2008-08-27

申请人： Scott Jay Crane ,  Simon J.S. McElrea ,  Scott McGrath ,  Weiping Pan ,  De Ann Melcher ,  Marc E. Robinson

发明人： Scott Jay Crane ,  Simon J.S. McElrea ,  Scott McGrath ,  Weiping Pan ,  De Ann Melcher ,  Marc E. Robinson

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L24/83 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/27452 ,  H01L2224/29005 ,  H01L2224/29006 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

摘要： A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

摘要翻译： 半导体管芯上的保形涂层提供了管芯和支撑件之间的粘附。 不需要额外的粘合剂将模具固定在支撑件上。 共形涂层在组装期间保护模具，并且用于使模具与模具可接触的导电部件电绝缘。 保形涂层可以是有机聚合物，例如聚对二甲苯。 此外，将模具粘附到可任选地是另一个模具的支撑件上的方法包括在模具和支撑件之间提供共形的涂层，以及加热模具和支撑件之间的涂层。 保形涂层可以设置在模具的表面的芯片附着区域上，或在支撑体的表面的模具安装区域上，或者在模具的表面的芯片附着区域上以及模具安装区域 的支撑体的表面; 并且可以在将模具放置在支撑件上之后提供保形涂层。

公开(公告)号：US6098278A

公开(公告)日：2000-08-08

申请号：US917447

申请日：1997-08-22

申请人： Alfons Vindasius ,  Marc E. Robinson ,  William R. Scharrenberg

发明人： Alfons Vindasius ,  Marc E. Robinson ,  William R. Scharrenberg

IPC分类号： H01L25/00 ,  H01L21/60 ,  H01L21/98 ,  H01L23/373 ,  H01L23/482 ,  H01L23/485 ,  H01L23/52 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06 ,  H01R4/04 ,  H01R29/00 ,  H05K3/30 ,  H05K3/32 ,  H05K7/02 ,  H05K3/36

CPC分类号： H01L24/81 ,  H01L23/3737 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01R29/00 ,  H01R4/04 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/753 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L29/0657 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49171

摘要： A flip chip on chip method for forming a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, a method for forming a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip. In still another preferred embodiment, a method of forming a flip chip assembly including a semiconductor wafer having a plurality of first flip-chips formed thereon; a plurality of second flip chips, each one of the second flip chips directly connected to a respective one of the plurality of first flip-chips; and electrically conductive epoxy means disposed between the respective first flip-chip and second flip-chip connections to form an electrical connection between the respective first flip-chip and second flip chip connections.

摘要翻译： 一种用于形成包括第一倒装芯片的倒装芯片组件的倒装芯片方法， 直接连接到第一倒装芯片的顶部的第二倒装芯片; 以及设置在所述第二倒装芯片和所述第一倒装芯片的顶部之间的导电环氧树脂装置，以在所述第一倒装芯片和所述第二倒装芯片之间形成电连接。 在另一个优选实施例中，一种用于形成包括多个半导体芯片的倒装芯片组件的方法，其中所述多个芯片彼此顶部垂直互连以形成电互连堆叠的芯片; 直接连接到芯片堆栈的顶部芯片的倒装芯片; 以及设置在所述倒装芯片和所述顶部芯片之间的导电环氧树脂装置，以在所述倒装芯片和所述顶部芯片之间形成电连接。 在另一个优选实施例中，一种形成倒装芯片组件的方法包括：半导体晶片，其上形成有多个第一倒装芯片; 多个第二倒装芯片，每个所述第二倒装芯片直接连接到所述多个第一倒装芯片中的相应一个; 以及设置在相应的第一倒装芯片和第二倒装芯片连接之间的导电环氧树脂装置，以在相应的第一倒装芯片和第二倒装芯片连接之间形成电连接。