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522 条记录 (耗时 0.027 秒)

    Self-aligned dual depth isolation and method of fabrication
    13.
    发明授权
    Self-aligned dual depth isolation and method of fabrication 失效
    自对准双深度隔离和制造方法

    公开(公告)号：US08587086B2

    公开(公告)日：2013-11-19

    申请号：US13598992

    申请日：2012-08-30

    申请人： Kangguo Cheng ,  Robert Heath Dennard ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Robert Heath Dennard ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L21/70

    CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/76283 ,  H01L27/1104

    摘要： FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

    摘要翻译： 提供了FDSOI器件及其制造方法。 一方面，一种制造装置的方法包括以下步骤。 提供具有基板，BOX和SOI层的晶片。 硬掩模层沉积在SOI层上。 光致抗蚀剂层沉积在硬掩模层上并且被图案化成一组片段。 执行倾斜的植入物以损坏被片段覆盖或遮蔽的硬掩模层的所有部分。 移除由植入物损坏的硬掩模层的部分。 通过硬掩模层执行第一蚀刻，以在SOI层，BOX和衬底的至少一部分中形成深沟槽。 使用图案化的光致抗蚀剂层对硬掩模层进行图案化。 通过硬掩模层进行第二蚀刻，以在SOI层中形成浅沟槽。

    Strained thin body CMOS device having vertically raised source/drain stressors with single spacer
    16.
    发明授权
    Strained thin body CMOS device having vertically raised source/drain stressors with single spacer 有权
    应变的薄体CMOS器件具有单个间隔物的垂直升高的源/漏应力源

    公开(公告)号：US08546228B2

    公开(公告)日：2013-10-01

    申请号：US12816399

    申请日：2010-06-16

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

    摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

    摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。

    Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers
    18.
    发明授权
    Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers 失效
    使用不同种类的应力层来增强NFET和PFET性能的结构和方法

    公开(公告)号：US08497168B2

    公开(公告)日：2013-07-30

    申请号：US13071940

    申请日：2011-03-25

    申请人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

    发明人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

    IPC分类号： H01L21/335 ,  H01L21/8232

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

    摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

    摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

    INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
    20.
    发明申请
    INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
    集成电路，包括DRAM和SRAM /逻辑

    公开(公告)号：US20130175595A1

    公开(公告)日：2013-07-11

    申请号：US13344885

    申请日：2012-01-06

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L27/108 ,  H01L21/336

    CPC分类号： H01L29/945 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207

    摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

    摘要翻译： 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。