公开(公告)号：US3303254A

公开(公告)日：1967-02-07

申请号：US29558263

申请日：1963-06-27

申请人： C B MESSENGER

发明人： SIMONS SANFORD L

IPC分类号： F16J3/00 ,  G03F1/20

CPC分类号： G03F1/20 ,  F16J3/00

公开(公告)号：US20240027889A1

公开(公告)日：2024-01-25

申请号：US18258453

申请日：2021-11-30

申请人： TOKYO OHKA KOGYO CO., LTD.

发明人： Kenichi YAMAUCHI ,  Kunihiro NODA ,  Dai SHIOTA

IPC分类号： G03F1/20 ,  C09D125/14 ,  C09D7/62 ,  C09D7/40 ,  C09D7/45 ,  H01L21/033

CPC分类号： G03F1/20 ,  C09D125/14 ,  C09D7/62 ,  C09D7/67 ,  C09D7/45 ,  H01L21/0332 ,  B82Y30/00

摘要： A metal oxide film-forming composition that yields a metal oxide film that exhibits a suppression of volume shrinkage in heating up to 400° C.; a method for producing metal oxide films that uses the metal oxide film-forming composition; and a method for reducing the volume shrinkage ratio of metal oxide films. The metal oxide film-forming composition includes metal oxide nanoclusters, a capping agent, a base material, and solvent. The size of the metal oxide nanoclusters is not more than 5 nm, and the capping agent includes at least one of alkoxysilanes, phenols, alcohols, carboxylic acids, and carboxylic acid halides. In the solid fraction of the metal oxide film-forming composition, the proportion of the mass of the inorganic fraction, with reference to the sum of the mass of the inorganic fraction and the mass of the organic fraction, is at least 25 mass %.

公开(公告)号：US11740546B2

公开(公告)日：2023-08-29

申请号：US17653665

申请日：2022-03-07

申请人： NuFlare Technology, Inc.

发明人： Tsubasa Nanao ,  Hiroshi Matsumoto

IPC分类号： H01J37/302 ,  H01J37/317 ,  H01J37/10 ,  G03F1/20 ,  G03F7/00

CPC分类号： G03F1/20 ,  G03F7/70641 ,  H01J37/10 ,  H01J37/302 ,  H01J37/3177 ,  H01J2237/1532 ,  H01J2237/21

摘要： In one embodiment, a multi charged particle beam writing apparatus includes an objective lens adjusting focus positions of multiple beams, an astigmatism correction element correcting astigmatism of the multiple beams, an inspection aperture allowing one of the multiple beams to pass therethrough, a deflector deflecting the multiple beams and causing the multiple beams to scan over the inspection aperture, a current detector detecting beam currents of the individual multiple beams after passing through the inspection aperture, a beam image formation unit forming a beam image based on the detected beam currents, a feature amount calculation unit generating a first waveform and a second waveform by adding brightnesses of the beam image in a first direction and in a second direction, and calculating a first and a second feature amounts from the first and the second waveforms, and a parameter calculation unit calculating an exciting parameter that is to be set for the astigmatism correction element based on the first feature amount and the second feature amount.

公开(公告)号：US20220299861A1

公开(公告)日：2022-09-22

申请号：US17653665

申请日：2022-03-07

申请人： NuFlare Technology, Inc.

发明人： Tsubasa NANAO ,  Hiroshi MATSUMOTO

IPC分类号： G03F1/20 ,  H01J37/302 ,  G03F7/20 ,  H01J37/10 ,  H01J37/317

摘要： In one embodiment, a multi charged particle beam writing apparatus includes an objective lens adjusting focus positions of multiple beams, an astigmatism correction element correcting astigmatism of the multiple beams, an inspection aperture allowing one of the multiple beams to pass therethrough, a deflector deflecting the multiple beams and causing the multiple beams to scan over the inspection aperture, a current detector detecting beam currents of the individual multiple beams after passing through the inspection aperture, a beam image formation unit forming a beam image based on the detected beam currents, a feature amount calculation unit generating a first waveform and a second waveform by adding brightnesses of the beam image in a first direction and in a second direction, and calculating a first and a second feature amounts from the first and the second waveforms, and a parameter calculation unit calculating an exciting parameter that is to be set for the astigmatism correction element based on the first feature amount and the second feature amount.

公开(公告)号：US20210200078A1

公开(公告)日：2021-07-01

申请号：US17083348

申请日：2020-10-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Chang LEE ,  Pei-Cheng HSU ,  Ta-Cheng LIEN ,  Wen-Chang HSUEH

IPC分类号： G03F1/24 ,  G03F1/54 ,  G03F1/20 ,  G03F1/48 ,  H01L21/033

摘要： A reflective mask blank includes a substrate, a reflective multilayer (RML) disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer has length or width dimensions smaller than the capping layer, and part of the capping layer is exposed by the absorber layer. The dimension of the absorber layer and the hard mask layer ranges between 146 cm to 148 cm. The dimensions of the substrate, the RML, and the capping layer range between 150 cm to 152 cm.

公开(公告)号：US10997355B1

公开(公告)日：2021-05-04

申请号：US16669808

申请日：2019-10-31

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Ahmed Hassan ,  James Culp

IPC分类号： G06F30/394 ,  G06F30/398 ,  H01L23/538 ,  G01N21/95 ,  G03F1/20 ,  G03F1/70 ,  H01J37/317

摘要： One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.

公开(公告)号：US10834828B2

公开(公告)日：2020-11-10

申请号：US15881205

申请日：2018-01-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Gerald Bartley ,  Darryl Becker ,  Matthew Doyle ,  Mark Jeanson

IPC分类号： G03F1/20 ,  G03F7/20 ,  H05K3/30 ,  H01F41/04 ,  H01F17/00 ,  H01F27/28 ,  G02B6/46 ,  H01B1/02 ,  H01F27/06 ,  H01G2/06 ,  H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  G03F1/00

摘要： A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

公开(公告)号：US10705420B2

公开(公告)日：2020-07-07

申请号：US15979751

申请日：2018-05-15

申请人： ASML US, LLC

发明人： Song Lan ,  Ke Zhao ,  Yang Cao ,  Jihui Huang

IPC分类号： G06F17/50 ,  G03F1/70 ,  G03F1/36 ,  G03F1/20 ,  G06T7/00

摘要： Directly biasing a mask image is disclosed. A method includes generating a mask image for the mask, biasing the mask image to obtain a biased mask image, and simulating the biased mask image to obtain a wafer image to be compared to the design pattern. Biasing the mask image includes updating at least one pixel of the mask image using an interpolation of neighboring pixels of the at least one pixel, the interpolation being dependent on a predetermined value.

公开(公告)号：US10553275B2

公开(公告)日：2020-02-04

申请号：US15949774

申请日：2018-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yangsyu Lin ,  Chiting Cheng ,  Jonathan Tsung-Yung Chang ,  Shang-Chi Wu

IPC分类号： G11C11/00 ,  G11C11/419 ,  G06F17/50 ,  H01L27/11 ,  G03F1/32 ,  G03F1/20 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36

摘要： A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.

公开(公告)号：US20190204727A1

公开(公告)日：2019-07-04

申请号：US15993936

申请日：2018-05-31

申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.

发明人： Lixuan CHEN

IPC分类号： G03F1/20 ,  G03F1/22

CPC分类号： G03F1/20 ,  G03F1/22

摘要： The present disclosure provides a photoresist and a preparation method thereof. The photoresist includes at least one kind of resin, a photoinitiator, a solvent, and at least one kind of scattering particle, and the at least one kind of scattering particle being configured to scatter ultraviolet light irradiated into the photoresist. The present disclosure may increase an exposure energy that the photoresist obtains during an exposure process, and thereby may reduce an exposure time required for the photoresist.