公开(公告)号：US11137684B2

公开(公告)日：2021-10-05

申请号：US16719118

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/54

Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.

公开(公告)号：US11112698B2

公开(公告)日：2021-09-07

申请号：US15723582

申请日：2017-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang Lilin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/004 ,  G03F7/30 ,  G03F7/38 ,  H01L21/027 ,  G03F7/42 ,  G03F7/20 ,  G03F7/09 ,  G03F7/095 ,  G03F7/039 ,  G03F7/40

Abstract: The present disclosure provides an embodiment of a method for lithography patterning. The method includes coating a photoresist layer over a substrate, wherein the photoresist layer includes a first polymer, and a first photo-acid generator (PAG), and a chemical additive mixed in a solvent; performing an exposing process to the photoresist layer; and performing a developing process to the photoresist layer to form a patterned photoresist layer. The chemical additive has a non-uniform distribution in the photoresist layer.

公开(公告)号：US11092899B2

公开(公告)日：2021-08-17

申请号：US16698044

申请日：2019-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Tung-Chin Wu ,  Shih-Hsiang Lo ,  Chih-Ming Lai ,  Jue-Chin Yu ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: G06F30/398 ,  G06F30/392 ,  G03F7/20 ,  G06F16/23 ,  G06N3/08 ,  G06N3/04

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

公开(公告)号：US11022886B2

公开(公告)日：2021-06-01

申请号：US15597734

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/16 ,  H01L21/02 ,  H01L21/321 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  G03F7/039 ,  G03F7/38 ,  H01L21/311

Abstract: The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.

公开(公告)号：US10796910B2

公开(公告)日：2020-10-06

申请号：US16731664

申请日：2019-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Han Ko ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  G03F7/26 ,  H01L21/033 ,  H01L21/308 ,  H01L21/266 ,  G03F7/038 ,  G03F7/20 ,  G03F7/40 ,  G03F7/09 ,  G03F7/039 ,  G03F7/38

Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.

公开(公告)号：US20200257203A1

公开(公告)日：2020-08-13

申请号：US16858846

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F7/40 ,  G03F7/38 ,  G03F7/039 ,  H01L21/67 ,  G03F7/16 ,  H01L21/02 ,  H01L21/027

Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.

公开(公告)号：US10720419B2

公开(公告)日：2020-07-21

申请号：US16522825

申请日：2019-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen Cho ,  Fu-Jye Liang ,  Chun-Kuang Chen ,  Chih-Tsung Shih ,  Li-Jui Chen ,  Po-Chung Cheng ,  Chin-Hsiang Lin

IPC: H01L27/02 ,  G03F1/36 ,  G06F30/30 ,  G06F30/39 ,  G06F30/20 ,  G06F119/18

Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.

公开(公告)号：US10684545B2

公开(公告)日：2020-06-16

申请号：US16021665

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  G03F7/11 ,  G03F7/004 ,  G03F7/20 ,  H01L29/66 ,  G03F7/32 ,  G03F7/038 ,  G03F7/09 ,  H01L21/266 ,  G03F7/38 ,  G03F7/039 ,  G03F7/075

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a assist layer over the material layer. The assist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, and a floating group bonded to the polymer backbone. The floating group includes carbon fluoride (CxFy). The method also includes forming a resist layer over the assist layer and patterning the resist layer.

公开(公告)号：US10672610B2

公开(公告)日：2020-06-02

申请号：US15600037

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L21/027 ,  G03F7/40

Abstract: A method for lithography patterning includes forming an opening in a first layer over a substrate and coating a grafting solution over the first layer and filling in the opening. The grafting solution comprises a grafting compound and a solvent. The grafting compound comprises a grafting unit chemically bonded to a linking unit chemically bonded to a polymer backbone. The linking unit comprises an alkyl segment. The grafting unit is attachable to the first layer. The method further includes curing the grafting solution so that a first portion of the grafting compound is attached to a surface of the first layer, thereby forming a second layer over the surface of the first layer.

公开(公告)号：US10649339B2

公开(公告)日：2020-05-12

申请号：US15482315

申请日：2017-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Ching Chang ,  Chen-Yu Liu ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F7/039 ,  G03F7/32 ,  G03F7/16 ,  G03F7/38

Abstract: A resist material and methods for forming a semiconductor structure including using the resist material are provided. The method for forming a semiconductor structure includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion of the resist layer by performing an exposure process. The method for forming a semiconductor structure further includes developing the resist layer in a developer. In addition, the resist layer is made of a resist material including a photosensitive polymer and a contrast promoter, and a protected functional group of the photosensitive polymer is deprotected to form a deprotected functional group during the exposure process, and a functional group of the contrast promoter bonds to the deprotected functional group of the photosensitive polymer.