公开(公告)号：US20160276009A1

公开(公告)日：2016-09-22

申请号：US14818809

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

IPC: G11C11/16 ,  G11C29/44

CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

公开(公告)号：US20160254318A1

公开(公告)日：2016-09-01

申请号：US14856316

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic random access memory (MRAM) bit cells employing source lines and/or bit lines disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.

Abstract translation: 公开了使用设置在多个堆叠金属层中的源极线和/或位线的磁性随机存取存储器（MRAM）位单元，以减少MRAM位单元电阻。 还公开了相关方法和系统。 在本文公开的方面，MRAM位单元被提供在存储器阵列中。 在集成电路（IC）中制造MRAM位单元，源极线和/或位线由设置在半导体层上方的多个堆叠金属层形成，以减小源极线的电阻。 以这种方式，如果IC中的节点尺寸按比例缩小，则可以维持或减小源极线和/或位线的电阻，以避免产生用于MRAM位的写入操作的写入电流的驱动电压的增加 细胞。

公开(公告)号：US09406354B1

公开(公告)日：2016-08-02

申请号：US14693755

申请日：2015-04-22

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/08 ,  G11C7/067 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26

Abstract: A read circuit for a memory cell may include an integrated logic circuit for sensing a current change. The integrated logic sensing circuit may be an offset cancelling single ended integrated logic sensing circuit. The circuit may include an offset canceling single ended sensing circuit coupled to a supply voltage, an offset canceling single ended sense amplifier circuit having a sense amplifier input coupled to the offset canceling single ended sensing circuit and a sense amplifier output, and a cell array coupled to a sensing circuit output and a ground.

Abstract translation: 用于存储单元的读取电路可以包括用于感测电流变化的集成逻辑电路。 集成逻辑感测电路可以是偏移消除单端集成逻辑感测电路。 电路可以包括耦合到电源电压的偏移消除单端感测电路，具有耦合到偏移消除单端感测电路的读出放大器输入和读出放大器输出的偏移消除单端读出放大器电路，以及耦合到 到感测电路输出和地。

公开(公告)号：US09379314B2

公开(公告)日：2016-06-28

申请号：US14109234

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a free layer. The MTJ also includes a barrier layer coupled to the free layer. The MTJ also has a fixed layer, coupled to the barrier layer. The fixed layer includes a first synthetic antiferromagnetic (SAF) multilayer having a first perpendicular magnetic anisotropy (PMA) and a first damping constant. The fixed layer also includes a second SAF multilayer having a second perpendicular magnetic anisotropy (PMA) and a second damping constant lower than the first damping constant. The first SAF multilayer is closer to the barrier layer than the second SAF multilayer. The fixed layer also includes a SAF coupling layer between the first and the second SAF multilayers.

Abstract translation: 磁隧道结（MTJ）装置包括自由层。 MTJ还包括耦合到自由层的阻挡层。 MTJ还具有耦合到阻挡层的固定层。 固定层包括具有第一垂直磁各向异性（PMA）和第一阻尼常数的第一合成反铁磁（SAF）多层。 固定层还包括具有第二垂直磁各向异性（PMA）和低于第一阻尼常数的第二阻尼常数的第二SAF多层。 第一SAF多层比第二SAF多层更靠近阻挡层。 固定层还包括在第一和第二SAF多层之间的SAF耦合层。

公开(公告)号：US20160049185A1

公开(公告)日：2016-02-18

申请号：US14460626

申请日：2014-08-15

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  G11C2213/78 ,  H01L27/228

Abstract: An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion.

Abstract translation: 一种装置包括差分MTJ对的第一磁隧道结（MTJ）装置。 该装置还包括差分MTJ对的第二MTJ装置。 第一MTJ装置包括具有高矫顽力部分的感测层。

公开(公告)号：US09142762B1

公开(公告)日：2015-09-22

申请号：US14229427

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Kangho Lee ,  Wei-Chuan Chen ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：US20150263266A1

公开(公告)日：2015-09-17

申请号：US14460731

申请日：2014-08-15

Applicant: QUALCOMM Incorporated

Inventor： Matthias Georg Gottwald ,  Chando Park ,  Xiaochun Zhu ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L43/08 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673

Abstract: An apparatus includes a perpendicular magnetic anisotropy magnetic tunnel junction (pMTJ) device. The pMTJ device includes a storage layer and a reference layer. The reference layer includes a portion configured to produce a ferrimagnetic effect. The portion includes a first layer, a second layer, and a third layer. The second layer is configured to antiferromagnetically (AF) couple the first layer and the third layer during operation of the pMTJ device.

Abstract translation: 一种装置包括垂直磁各向异性磁隧道结（pMTJ）装置。 pMTJ设备包括存储层和参考层。 参考层包括被配置为产生亚铁磁效应的部分。 该部分包括第一层，第二层和第三层。 第二层被配置为在pMTJ器件的操作期间反铁磁（AF）耦合第一层和第三层。

公开(公告)号：US20140206104A1

公开(公告)日：2014-07-24

申请号：US14219026

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/222 ,  H01L41/12 ,  H01L43/08 ,  H01L43/10

Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.

Abstract translation: 使用在MTJ上引起定向静态应变/应力以增加垂直磁各向异性的工艺和结构构造来构造部分垂直磁各向异性（PPMA）型磁性随机存取存储器单元。 因此，MTJ的开关电流降低。 在制造过程中，受控方向和/或受控幅度诱发MTJ上的定向静态应变/应力。 MTJ永久地受到预定的定向应力，并且永久地包括提供减小的开关电流的定向静态应变/应变。

公开(公告)号：US20140119097A1

公开(公告)日：2014-05-01

申请号：US14147817

申请日：2014-01-06

Applicant: QUALCOMM Incorporated

Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

公开(公告)号：US20140073064A1

公开(公告)日：2014-03-13

申请号：US14086054

申请日：2013-11-21

Applicant: QUALCOMM Incorporated

Inventor： Seung Hyuk Kang ,  Xia Li ,  Wei-Chuan Chen ,  Kangho Lee ,  Xiaochun Zhu ,  Wah Nam Hsu

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

Abstract translation: 具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外，可以在MTJ层之前的底部电极上沉​​积底层以促进MTJ的期望特性。