公开(公告)号：US07886204B2

公开(公告)日：2011-02-08

申请号：US11535853

申请日：2006-09-27

Applicant: Carlos J. Gonzalez ,  Daniel C. Guterman

Inventor： Carlos J. Gonzalez ,  Daniel C. Guterman

IPC: G11C11/4193 ,  G11C16/28

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C29/028 ,  G11C29/42 ,  G11C29/46 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract translation: 提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。 如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。 基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

公开(公告)号：US07839685B2

公开(公告)日：2010-11-23

申请号：US12572098

申请日：2009-10-01

Applicant: Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

Inventor： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract translation: 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

公开(公告)号：US07834392B2

公开(公告)日：2010-11-16

申请号：US12510077

申请日：2009-07-27

Applicant: Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

Inventor： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

Abstract translation: 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

公开(公告)号：US07821835B2

公开(公告)日：2010-10-26

申请号：US11936081

申请日：2007-11-07

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common selection line to maintain the first condition for a particular non-volatile storage element associated with the bit line and common selection line. A second value is applied to the bit line and at least a subset of the word lines are boosted to create a second condition for a different non-volatile storage element associated with the bit line and common selection line. The second condition is based on the second value. The first condition and the second condition overlap in time. Both non-volatile storage elements are programmed concurrently, based on their associated conditions.

Abstract translation: 本发明的一个实施例包括将第一值应用于位线，升高与位线相关联的字线和公共选择线，以基于第一值创建第一条件，并切断边界非易失性存储元件 与公共选择线相关联，以维持与位线和公共选择线相关联的特定非易失性存储元件的第一条件。 将第二值应用于位线，并且提高字线的至少一个子集以为与位线和公共选择线相关联的不同非易失性存储元件创建第二条件。 第二个条件是基于第二个值。 第一个条件和第二个条件在时间上重叠。 这两个非易失性存储元件都是根据其相关条件同时编程的。

公开(公告)号：US20100205360A1

公开(公告)日：2010-08-12

申请号：US12765737

申请日：2010-04-22

Applicant: Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

Inventor： Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

IPC: G06F12/02 ,  G06F13/00 ,  H04L9/30

CPC classification number: G06F13/4068 ,  G06K19/07741 ,  H05K5/0265 ,  H05K5/0282

Abstract: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

公开(公告)号：US07760555B2

公开(公告)日：2010-07-20

申请号：US11752008

申请日：2007-05-22

Applicant: Daniel C. Guterman ,  Stephen J. Gross ,  Shahzad Khalid ,  Geoffrey S. Gongwer

Inventor： Daniel C. Guterman ,  Stephen J. Gross ,  Shahzad Khalid ,  Geoffrey S. Gongwer

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C16/349

Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

Abstract translation: 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

公开(公告)号：US07747927B2

公开(公告)日：2010-06-29

申请号：US11285992

申请日：2005-11-22

Applicant: Daniel C. Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Lourenco Barrocas ,  Carlos Gonzalez ,  Kevin M. Conley

Inventor： Daniel C. Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Lourenco Barrocas ,  Carlos Gonzalez ,  Kevin M. Conley

IPC: G11C29/00 ,  H03M13/00

CPC classification number: G06F13/1694 ,  G06F11/1068 ,  G11C7/00

Abstract: A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

Abstract translation: 非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。 以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。 特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

公开(公告)号：US07716538B2

公开(公告)日：2010-05-11

申请号：US11535879

申请日：2006-09-27

Applicant: Carlos J. Gonzalez ,  Daniel C. Guterman

Inventor： Carlos J. Gonzalez ,  Daniel C. Guterman

IPC: G11C11/4193 ,  G11C16/28

CPC classification number: G11C16/349 ,  G11C16/04 ,  G11C2029/0411

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract translation: 提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。 如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。 基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

公开(公告)号：US07584391B2

公开(公告)日：2009-09-01

申请号：US11759872

申请日：2007-06-07

Applicant: Geoffrey S. Gongwer ,  Daniel C. Guterman ,  Yupin Kawing Fong

Inventor： Geoffrey S. Gongwer ,  Daniel C. Guterman ,  Yupin Kawing Fong

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C11/5635 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

Abstract translation: 提出了一种“智能验证”技术，其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现来编程多状态存储器。 这种技术可以通过提供“智能”手段来使顺序验证的多状态存储器实现中的可靠操作增加多状态写入速度，从而最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量。 在程序/验证周期序列的开始，在验证阶段只检查最低的状态或状态。 当达到较低的状态时，额外的更高的状态被添加到验证序列中，并且可以去除较低的状态。

公开(公告)号：US07570518B2

公开(公告)日：2009-08-04

申请号：US11936084

申请日：2007-11-07

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common selection line to maintain the first condition for a particular non-volatile storage element associated with the bit line and common selection line. A second value is applied to the bit line and at least a subset of the word lines are boosted to create a second condition for a different non-volatile storage element associated with the bit line and common selection line. The second condition is based on the second value. The first condition and the second condition overlap in time. Both non-volatile storage elements are programmed concurrently, based on their associated conditions.

Abstract translation: 本发明的一个实施例包括将第一值应用于位线，升高与位线相关联的字线和公共选择线，以基于第一值创建第一条件，并切断边界非易失性存储元件 与公共选择线相关联，以维持与位线和公共选择线相关联的特定非易失性存储元件的第一条件。 将第二值应用于位线，并且提高字线的至少一个子集以为与位线和公共选择线相关联的不同非易失性存储元件创建第二条件。 第二个条件是基于第二个值。 第一个条件和第二个条件在时间上重叠。 这两个非易失性存储元件都是根据其相关条件同时编程的。