公开(公告)号：US10163818B2

公开(公告)日：2018-12-25

申请号：US15495788

申请日：2017-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Jing-Cheng Lin ,  Tsei-Chung Fu

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L33/62 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L23/525

摘要： A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.

公开(公告)号：US10163706B2

公开(公告)日：2018-12-25

申请号：US14586276

申请日：2014-12-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC分类号： H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L23/544 ,  H01L23/00 ,  H01L23/498

摘要： A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

公开(公告)号：US10153175B2

公开(公告)日：2018-12-11

申请号：US14697380

申请日：2015-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC分类号： H01L23/498 ,  H01L23/532 ,  H01L23/31 ,  H01L21/321 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/525

摘要： Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US10128175B2

公开(公告)日：2018-11-13

申请号：US13753328

申请日：2013-01-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L25/03 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/538

摘要： Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device.

公开(公告)号：US10115650B2

公开(公告)日：2018-10-30

申请号：US15180892

申请日：2016-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L23/433 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L21/78 ,  H01L21/60

摘要： A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

公开(公告)号：US10115647B2

公开(公告)日：2018-10-30

申请号：US14658968

申请日：2015-03-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Lin Huang ,  Jung-Hua Chang ,  Jy-Jie Gau ,  Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065

摘要： A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.

公开(公告)号：US20180286839A1

公开(公告)日：2018-10-04

申请号：US16002791

申请日：2018-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao Tsai ,  Feng-Cheng Hsu ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC分类号： H01L25/10 ,  H01L21/768 ,  H01L21/822 ,  H01L23/31 ,  H01L21/56 ,  H01L25/11

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/8221 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00

摘要： A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the butter layer, wherein the guiding trench is misaligned with the device die.

公开(公告)号：US10083946B2

公开(公告)日：2018-09-25

申请号：US15495017

申请日：2017-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao Tsai ,  Feng-Cheng Hsu ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L25/11

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/8221 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00

摘要： A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

公开(公告)号：US10079225B2

公开(公告)日：2018-09-18

申请号：US15493985

申请日：2017-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Li-Hui Cheng

IPC分类号： H01L21/768 ,  H01L23/552 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC分类号： H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24146 ,  H01L2224/24991 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.

公开(公告)号：US10079159B2

公开(公告)日：2018-09-18

申请号：US15192310

申请日：2016-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Li-Hui Cheng

IPC分类号： H01L21/768 ,  H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L25/10 ,  H01L21/56 ,  H01L23/528

CPC分类号： H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24146 ,  H01L2224/24991 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.