公开(公告)号：US20240017538A1

公开(公告)日：2024-01-18

申请号：US18363750

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Jie Huang ,  Yu-Ching Lo ,  Ching-Pin Yuan ,  Wen-Chih Lin ,  Cheng-Yu Kuo ,  Yi-Yang Lei ,  Ching-Hua Hsieh

IPC: B32B38/18 ,  H01L23/00 ,  H01L21/48

CPC classification number: B32B38/1858 ,  H01L24/96 ,  H01L21/4857

Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

公开(公告)号：US11764127B2

公开(公告)日：2023-09-19

申请号：US17185966

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Chun Liao ,  Sung-Yueh Wu ,  Chien-Ling Hwang ,  Ching-Hua Hsieh

IPC: H01L23/48 ,  H01L23/15 ,  H01L21/768 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

公开(公告)号：US11756872B2

公开(公告)日：2023-09-12

申请号：US17199348

申请日：2021-03-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Yueh Wu ,  Chien-Ling Hwang ,  Jen-Chun Liao ,  Ching-Hua Hsieh ,  Pei-Hsuan Lee ,  Chia-Hung Liu

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253

Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.

公开(公告)号：US20230268316A1

公开(公告)日：2023-08-24

申请号：US17674847

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Yueh Wu ,  Chien-Ling Hwang ,  Jen-Chun Liao ,  Ching-Hua Hsieh

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/3114 ,  H01L21/561 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81947

Abstract: A package structure includes a semiconductor device including a conductive feature, a joint layer, a pillar structure, an encapsulant and a RDL structure. The joint layer is disposed on the conductive feature. The pillar structure is disposed on and coupled to the semiconductor device through the joint layer. The encapsulant laterally encapsulates the semiconductor device and the pillar structure. The RDL structure is electrically connected to the semiconductor device.

公开(公告)号：US20230035212A1

公开(公告)日：2023-02-02

申请号：US17389313

申请日：2021-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Chiang ,  Chao-wei Li ,  Wei-Lun Tsai ,  Chia-Min Lin ,  Yi-Da Tsai ,  Sheng-Feng Weng ,  Yu-Hao Chen ,  Sheng-Hsiang Chiu ,  Chih-Wei Lin ,  Ching-Hua Hsieh

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L25/00

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

公开(公告)号：US20220384288A1

公开(公告)日：2022-12-01

申请号：US17884499

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US20220367310A1

公开(公告)日：2022-11-17

申请号：US17320198

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Hsuan Lee ,  Ching-Hua Hsieh ,  Chien-Ling Hwang

IPC: H01L23/36 ,  H01L23/40 ,  H01L21/50

Abstract: A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.

公开(公告)号：US20220314595A1

公开(公告)日：2022-10-06

申请号：US17395440

申请日：2021-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Jie Huang ,  Yu-Ching Lo ,  Ching-Pin Yuan ,  Wen-Chih Lin ,  Cheng-Yu Kuo ,  Yi-Yang Lei ,  Ching-Hua Hsieh

IPC: B32B38/18 ,  H01L21/48 ,  H01L23/00

Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

公开(公告)号：US20220223542A1

公开(公告)日：2022-07-14

申请号：US17148572

申请日：2021-01-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Chun-Yen Lan ,  Tzu-Ting Chou ,  Tzu-Shiun Sheu ,  Chih-Wei Lin ,  Shih-Peng Tai ,  Wei-Cheng Wu ,  Ching-Hua Hsieh

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

公开(公告)号：US11171090B2

公开(公告)日：2021-11-09

申请号：US16411639

申请日：2019-05-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun Yi Wu ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Shou-Yi Wang ,  Chien-Hsun Chen

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L21/78 ,  H01L23/532 ,  H01L21/60

Abstract: A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.