公开(公告)号：US20200075753A1

公开(公告)日：2020-03-05

申请号：US16116685

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/66 ,  H01L21/768

Abstract: Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies.

公开(公告)号：US10522367B2

公开(公告)日：2019-12-31

申请号：US15450605

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L21/265 ,  H01L21/322 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

公开(公告)号：US20190378904A1

公开(公告)日：2019-12-12

申请号：US16002459

申请日：2018-06-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Ye Lu ,  Lixin Ge

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

公开(公告)号：US10483287B1

公开(公告)日：2019-11-19

申请号：US16138084

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/08

Abstract: Transistors formed on semiconductor substrates are not well-suited for integrated circuits employed in media designed to structurally flex to conform to a shaped surface or in response to physical stress. Structural flexing of wearable electronic devices, such as clothing, may cause cracking in the semiconductor substrate, resulting in failure of the integrated circuits. TFTs formed on flexible substrates can withstand structural flexing without failure. CMOS circuits are employed due to cost, performance, and power efficiency considerations. To provide increased drive strength for such applications, a flexible TFT structure for a CMOS circuit disclosed herein includes an exemplary NFET integrated with a complementary PFET on a flexible substrate. By forming a top gate on a semiconductor layer of a FET opposite to a bottom gate formed between the semiconductor layer and the flexible substrate, an effective thickness of an inversion channel layer induced in the semiconductor layer is doubled.

公开(公告)号：US10431581B1

公开(公告)日：2019-10-01

申请号：US15966225

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/205 ,  H01L29/225 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/737

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a well region disposed adjacent to the substrate, a first fin disposed above the well region, a second fin disposed above the substrate, and a gate region disposed adjacent to each of the first fin and the second fin. The semiconductor device may also include at least one third fin disposed above the substrate, a support layer disposed above the at least one third fin, and a compound semiconductor device disposed above the support layer.

公开(公告)号：US10354955B2

公开(公告)日：2019-07-16

申请号：US15687362

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Junjing Bao

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  C01B32/182 ,  H01L29/78 ,  H01L21/8234

Abstract: An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

公开(公告)号：US10312244B2

公开(公告)日：2019-06-04

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US10283650B2

公开(公告)日：2019-05-07

申请号：US15659718

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/66 ,  H01L29/93 ,  H01L29/06

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.

公开(公告)号：US10164054B2

公开(公告)日：2018-12-25

申请号：US15683530

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/768 ,  H01L29/812

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US10109724B2

公开(公告)日：2018-10-23

申请号：US15614471

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li ,  Miguel Miranda Corbalan

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.