公开(公告)号：US10833254B2

公开(公告)日：2020-11-10

申请号：US16431490

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC: H01L43/06 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01F10/32

Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

公开(公告)号：US10740017B2

公开(公告)日：2020-08-11

申请号：US15963668

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Wei-Chuan Chen ,  Sungryul Kim ,  Adam Edward Newham ,  Seung Hyuk Kang ,  Rashid Ahmed Akbar Attar

IPC: G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372 ,  H04W4/80

Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

公开(公告)号：US20200066968A1

公开(公告)日：2020-02-27

申请号：US16107484

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Sungryul Kim ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  H01L27/22

Abstract: Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.

公开(公告)号：US10483457B1

公开(公告)日：2019-11-19

申请号：US16102941

申请日：2018-08-14

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  G11C11/56 ,  G11C11/18 ,  G11C11/16

Abstract: Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

公开(公告)号：US20190342106A1

公开(公告)日：2019-11-07

申请号：US15969043

申请日：2018-05-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Nicholas Ka Ming Stevens-Yu

IPC: H04L9/32 ,  G11C11/419 ,  G11C11/418 ,  G06F21/75

Abstract: Physically unclonable function (PUF) circuits employing multiple PUF memories to decouple a PUF challenge input from a PUF response output for enhanced security. The PUF circuit includes a PUF challenge memory and a PUF response memory. In response to a read operation, the PUF challenge memory uses a received PUF challenge input data word to address PUF challenge memory arrays therein to generate a plurality of intermediate PUF challenge output data words. The PUF response memory is configured to generate a second, final PUF response output data word in response to intermediate PUF challenge output data words. In this manner, it is more difficult to learn the challenge-response behavior of the PUF circuit, because the PUF challenge input data word does not directly address a memory array that stores memory states representing final logic values in the PUF response output data word.

公开(公告)号：US10460780B2

公开(公告)日：2019-10-29

申请号：US15939923

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

公开(公告)号：US10224368B2

公开(公告)日：2019-03-05

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: G11C11/00 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US20190006415A1

公开(公告)日：2019-01-03

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10134808B2

公开(公告)日：2018-11-20

申请号：US15137437

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Chando Park ,  Matthias Georg Gottwald ,  Seung Hyuk Kang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Magnetic tunnel junction (MTJ) devices with a heterogeneous free layer structure particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer section provided below a first tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer section includes one pinned layer magnetized in one magnetic orientation. In another aspect, a second pinned layer section and a second TMR barrier layer are provided above a free layer section and above the first TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel (AP) to that of the first pinned layer section. In yet another aspect, the free layer comprises first and second heterogeneous layers separated by an anti-ferromagnetic coupling spacer, the first and second heterogeneous layers differing in their magnetic anisotropy.

公开(公告)号：US10102898B2

公开(公告)日：2018-10-16

申请号：US15829004

申请日：2017-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Seung Hyuk Kang

IPC: G11C11/22 ,  G11C13/00 ,  H01L21/02 ,  H01L27/1159 ,  H01L29/49 ,  H01L29/47 ,  H01L29/51 ,  H01L29/16 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/786

Abstract: Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.