公开(公告)号：US10324721B2

公开(公告)日：2019-06-18

申请号：US15488947

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G11C11/00 ,  G06F9/30 ,  G11C17/18 ,  G11C17/16 ,  G06F13/40 ,  G11C11/4094 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US10304154B2

公开(公告)日：2019-05-28

申请号：US15495054

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US10303953B2

公开(公告)日：2019-05-28

申请号：US15488555

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Mayuresh M. Varerkar ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Sherine Abdelhak ,  Sachin Godse ,  Farshad Akhbari ,  Narayan Srinivasa ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Dukhwan Kim ,  Feng Chen ,  Abhishek R. Appu ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: H04N5/225 ,  H04N3/20 ,  G06K9/00 ,  G06T1/20 ,  H04N5/228 ,  H04N7/14 ,  H04N5/38

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

公开(公告)号：US10261903B2

公开(公告)日：2019-04-16

申请号：US15489149

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190109582A1

公开(公告)日：2019-04-11

申请号：US16180604

申请日：2018-11-05

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Anupama A. Thaploo ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/21

CPC classification number: H03K3/012 ,  H03K3/356 ,  H03K3/35606 ,  H03K19/215

Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

公开(公告)号：US20190102860A1

公开(公告)日：2019-04-04

申请号：US15720385

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Altug Koker ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/0811 ,  H04W52/02 ,  G06T1/20

Abstract: Methods and apparatus relating to tile-aware sector cache for graphics are described. One embodiment enables a sector cache implementation (e.g., in graphics implementations) to reduce the size of the tag space. The reduction in tag space, in turn, reduces power consumption, (e.g., via reduced ways). Moreover, cache efficiency is maintained by keeping the sector utilization at a high rate in one or more embodiments. Other embodiments are also disclosed and claimed.

公开(公告)号：US10191759B2

公开(公告)日：2019-01-29

申请号：US15025735

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： David J. Cowperthwaite ,  Murali Ramadoss ,  Ankur N. Shah ,  Balaji Vembu ,  Altug Koker ,  Aditya Navale

IPC: G06F9/455 ,  G06F9/50 ,  G06T1/20

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

公开(公告)号：US10146691B2

公开(公告)日：2018-12-04

申请号：US15374630

申请日：2016-12-09

Applicant: INTEL CORPORATION

Inventor： Hashem Hashemi ,  Saurabh Sharma ,  Altug Koker

IPC: G06F12/16 ,  G06F12/0842

Abstract: One embodiment provides for a memory system comprising a cache memory and a cache control circuit to receive a request to perform a partial cache line write to a first cache line of the cache memory, merge the request to perform the partial cache line write with a pending request to write to the first cache line, and process a merged request as a full cache line write.

公开(公告)号：US20180315399A1

公开(公告)日：2018-11-01

申请号：US15819152

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G09G5/36 ,  G06T1/20 ,  G09G5/393 ,  G06N99/00 ,  G06T15/00

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3851 ,  G06F2207/3824 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N20/00 ,  G06T15/005 ,  G09G5/393

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

公开(公告)号：US20180315398A1

公开(公告)日：2018-11-01

申请号：US15787129

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G09G5/36 ,  G06T1/20 ,  G09G5/393

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3851 ,  G06F2207/3824 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N20/00 ,  G06T15/005 ,  G09G5/393

Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.