公开(公告)号：US6049899A

公开(公告)日：2000-04-11

申请号：US113800

申请日：1998-07-08

Applicant: Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

Inventor： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC: G06F11/10 ,  G11C16/10 ,  G11C29/50 ,  G11C29/52 ,  H03M13/00

CPC classification number: G11C29/028 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

公开(公告)号：US5910915A

公开(公告)日：1999-06-08

申请号：US65512

申请日：1998-04-23

Applicant: Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

Inventor： Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

IPC: G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885 ,  G11C2211/5634

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

Abstract translation: 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

公开(公告)号：US5847425A

公开(公告)日：1998-12-08

申请号：US341411

申请日：1994-11-17

Applicant: Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

Inventor： Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

公开(公告)号：US5380672A

公开(公告)日：1995-01-10

申请号：US117219

申请日：1993-09-03

Applicant: Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

Inventor： Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract translation: PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供 它们之间的电容耦合垂直形成。 这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。 此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

公开(公告)号：US5343063A

公开(公告)日：1994-08-30

申请号：US629250

申请日：1990-12-18

Applicant: Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

Inventor： Jack H. Yuan ,  Gheorghe Samachisa ,  Daniel C. Guterman ,  Eliyahou Harari

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  H01L29/78

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract translation: PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供 它们之间的电容耦合垂直形成。 这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。 此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

公开(公告)号：US4980859A

公开(公告)日：1990-12-25

申请号：US335112

申请日：1989-04-07

Applicant: Daniel C. Guterman ,  Isao Nojima ,  Ping Wang

Inventor： Daniel C. Guterman ,  Isao Nojima ,  Ping Wang

IPC: G11C17/00 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C14/00

Abstract: A nonvolatile, semiconductor randon access memory cell comprising a static RAM element and a nonvolatile memory element having differential charge storage capabilities is presented. The static RAM and nonvolatile memory elements are interconnected to allow information to be exchanged between two elements, thus allowing the faster static RAM element to serve as the primary memory to the system and allowing the nonvolatile memory element to serve as permanent storage during power-down conditions. In one embodiment, the nonvolatile memory element comprises two electrically erasable PROM devices (EEPROMs). The two EEPROM devices store differential charges corresponding to the complementary outputs of the static RAM element. The nature of the differential charge storage allows lower programming voltages to be used on the EEPROM devices, resulting in increased storage intergrity and increased endurance of the EEPROM devices.

Abstract translation: 提供了一种包括静态RAM元件和具有差分电荷存储能力的非易失性存储元件的非易失性半导体随机存取存储单元。 静态RAM和非易失性存储器元件互连以允许在两个元件之间交换信息，从而允许更快的静态RAM元件用作系统的主要存储器，并允许非易失性存储器元件在断电期间用作永久存储器 条件。 在一个实施例中，非易失性存储元件包括两个电可擦除PROM器件（EEPROM）。 两个EEPROM器件存储对应于静态RAM元件的互补输出的差分电荷。 差分电荷存储器的性质允许在EEPROM器件上使用更低的编程电压，从而增加了EEPROM器件的存储整合性和更高的耐用性。

公开(公告)号：US4752912A

公开(公告)日：1988-06-21

申请号：US757643

申请日：1985-07-22

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: H01L29/66825 ,  G11C16/0433 ,  H01L21/28273 ,  H01L29/7883

Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described as including four electrode layers, one of which being formed as a substrate coupling electrode. The cell is also described as being relatively process intolerant. The first electrode layer above the substrate is used to mask the diffusion or implantation of the substrate coupling electrode and other regions in the substrate to form self-aligned active devices.

Abstract translation: 用三层多晶硅制造紧凑的浮动栅极，非易失性的，电可改变的存储器件。 在非易失性存储器阵列中，每个单元与其它单元电隔离以消除存储器阵列的非寻址单元中的数据干扰状况。 存储单元和阵列被描述为包括四个电极层，其中一个电极层被形成为衬底耦合电极。 细胞也被描述为相对过程不耐受。 衬底上方的第一电极层用于掩盖衬底耦合电极和衬底中的其它区域的扩散或注入以形成自对准有源器件。

公开(公告)号：US4599706A

公开(公告)日：1986-07-08

申请号：US734478

申请日：1985-05-14

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: G11C16/0433 ,  H01L29/7883

Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described in a first embodiment as including four electrode layers, one of which being formed as a substrate coupling electrode. A second embodiment includes a three electrode layer device wherein the need for the substrate coupling electrode is eliminated.

Abstract translation: 用三层多晶硅制造紧凑的浮动栅极，非易失性的，电可改变的存储器件。 在非易失性存储器阵列中，每个单元与其它单元电隔离以消除存储器阵列的非寻址单元中的数据干扰状况。 存储单元和阵列在第一实施例中被描述为包括四个电极层，其中一个电极层被形成为衬底耦合电极。 第二实施例包括消除对基板耦合电极的需要的三电极层器件。

公开(公告)号：US4422092A

公开(公告)日：1983-12-20

申请号：US344289

申请日：1982-02-01

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L27/02

CPC classification number: H01L27/11519 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7885

Abstract: An electrically programmable read only memory (EPROM) of the floating gate type is constructed having an improved coupling ratio made by allowing the edges of the floating gates to be self aligned with the edges of the control gates. The ratio of the capacitance between the floating gate and control gate is increased by extending the floating gate out over the source and drain.

Abstract translation: 浮栅型的电可编程只读存储器（EPROM）被构造成具有通过允许浮置栅极的边缘与控制栅极的边缘自对准而改进的耦合比。 浮置栅极和控制栅极之间的电容比通过在源极和漏极上延伸出浮栅而增加。

公开(公告)号：US08014197B2

公开(公告)日：2011-09-06

申请号：US12604904

申请日：2009-10-23

Applicant: Nima Mokhlesi ,  Daniel C. Guterman

Inventor： Nima Mokhlesi ,  Daniel C. Guterman

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621

Abstract: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.

Abstract translation: 提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。 多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。 随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。 这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。 根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。