公开(公告)号：US4526632A

公开(公告)日：1985-07-02

申请号：US465176

申请日：1983-02-09

申请人： Jun-ichi Nishizawa ,  Kazuomi Ito ,  Yasuo Okuno

发明人： Jun-ichi Nishizawa ,  Kazuomi Ito ,  Yasuo Okuno

IPC分类号： C30B31/04 ,  H01L21/368 ,  H01L21/383 ,  H01L21/385 ,  H01L21/40 ,  H01L29/227 ,  H01L33/28 ,  H01L33/40 ,  H01L21/208 ,  H01L21/223

CPC分类号： H01L33/0083 ,  C30B29/48 ,  C30B31/04 ,  H01L21/02409 ,  H01L21/02551 ,  H01L21/0256 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02625 ,  H01L21/02628 ,  H01L21/383 ,  H01L21/385 ,  H01L21/40 ,  H01L29/227

摘要： A method of forming a pn junction with a Group IIB-VIB compound semiconductor containing Zn is disclosed, the method including preparing an n type semiconductor region either locally or entirely in a Group IIB-VIB compound semiconductor crystal obtained by relying on a crystal growth method in liquid phase using a temperature difference technique, and subjecting this crystal to a thermal annealing in a Zn solution or in a Zn atmosphere to produce an n type region. Crystal growth is conducted while controlling the vapor pressure of the constituent Group IVB element to produce a p type region. A combination of all these steps gives a more stable pn junction.

摘要翻译： 公开了一种与含有Zn的IIB-VIB族化合物半导体形成pn结的方法，该方法包括在依赖于晶体生长方法获得的IIB-VIB族化合物半导体晶体中局部或全部制备n型半导体区域 使用温差技术在液相中，并使该晶体在Zn溶液或Zn气氛中进行热退火以产生n型区域。 在控制构成IVB族元素的蒸汽压的同时进行晶体生长以产生p型区域。 所有这些步骤的组合给出了更稳定的pn结。

公开(公告)号：US4470059A

公开(公告)日：1984-09-04

申请号：US369606

申请日：1982-04-19

申请人： Jun-ichi Nishizawa ,  Tadahiro Ohmi

发明人： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC分类号： H01L29/80 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/739 ,  H01L29/772

CPC分类号： H01L29/0653 ,  H01L29/1066 ,  H01L29/20 ,  H01L29/739 ,  H01L29/7722

摘要： A gallium arsenide static induction transistor of normally-off type simple in manufacture and exhibiting a superior function and suitable for use in low and medium power operation in integrated circuit is obtained by arranging so that its channel region has a length l (.mu.m), a width (.mu.m) and an impurity concentration N (cm.sup.-3), and that the ratio l/w is 0.5-5.0 and that the product Nw.sup.2 is not larger than 2.5.times.10.sup.15 cm.sup.-3..mu.m.sup.2.

摘要翻译： 通过布置使得其通道区域具有长度l（μm），获得了常规关闭型砷化镓静电感应晶体管，其制造简单并且表现出优异的功能并且适用于集成电路中的低功率和中等功率操作， 宽度（μm）和杂质浓度N（cm-3），比率l / w为0.5-5.0，产品Nw2不大于2.5×10 15 cm -3。 亩。

公开(公告)号：US4400710A

公开(公告)日：1983-08-23

申请号：US210531

申请日：1980-11-25

申请人： Jun-ichi Nishizawa ,  Tadahiro Ohmi ,  Keishiro Takahashi

发明人： Jun-ichi Nishizawa ,  Tadahiro Ohmi ,  Keishiro Takahashi

IPC分类号： H01L21/331 ,  H01L29/68 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/80 ,  H01L29/48

CPC分类号： H01L29/7839 ,  H01L29/739 ,  H01L29/7392 ,  H01L29/80 ,  H01L29/806

摘要： A semiconductor device having its carrier-injecting region formed with a Schottky structure, and arranged so that the current flowing through the Schottky barrier by virtue of tunnel effect is controlled by a controlling electrode to thereby control the drain or collector or anode current. Thus, this device has a large current density and a large current gain. This device can be used not only as a discrete one, but also it is quite suitable when applied to integrated circuits.

摘要翻译： 一种半导体器件，其载流子注入区域形成肖特基结构，并配置为通过控制电极控制流过肖特基势垒的电流，从而控制漏极或集电极或阳极电流。 因此，该器件具有大的电流密度和大的电流增益。 该器件不仅可以作为离散器件使用，而且还适用于集成电路。

公开(公告)号：US4377817A

公开(公告)日：1983-03-22

申请号：US130775

申请日：1980-03-17

申请人： Jun-ichi Nishizawa ,  Tadahiro Ohmi

发明人： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC分类号： H01L29/80 ,  H01L27/146 ,  H01L31/112 ,  H04N5/335 ,  H04N5/374

CPC分类号： H01L31/1126 ,  H01L27/1464 ,  H01L27/14679

摘要： This invention relates to a semiconductor image sensors and more particularly, to a back-illuminated-type static induction transistor image sensors.FIGS. 4A to 4C show the back illuminated type SIT image sensors operating in the electron depletion storing mode, where the n.sup.+ buried floating region 23 serves as storage region.

摘要翻译： 本发明涉及一种半导体图像传感器，更具体地说，涉及背照式静电感应晶体管图像传感器。 图 图4A至4C示出了以电子耗尽存储模式操作的背照式SIT图像传感器，其中n +掩埋浮动区域23用作存储区域。

公开(公告)号：US4364072A

公开(公告)日：1982-12-14

申请号：US18774

申请日：1979-03-08

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： H01L29/10 ,  H01L29/739 ,  H01L29/772 ,  H01L29/80

CPC分类号： H01L29/7392 ,  H01L29/1025 ,  H01L29/7722

摘要： In a static induction type semiconductor device comprising a semiconductor region having one conductivity type and a low impurity concentration and gate regions having an opposite conductivity type and a high impurity concentration formed in the semiconductor region to thereby define a channel region between these gate regions, there is provided a subsidiary semiconductor region having the one conductivity type and a relatively high impurity concentration either around each gate region to leave an effective channel region in the semiconductor region, or adjacent to the effective channel region in the entire channel region on the drain side. By so constructing the device, this effective channel region has a relatively low potential difference even when the channel region is completely depleted, and provides a relatively wide current path. The subsidiary semiconductor regions establish a relatively high potential difference near the gate regions so that the distance between the gate regions can be made substantially small. In case the subsidiary semiconductor regions are provided around the gate regions, the built-in potential at the junction will become large so that, even at the time of forward biasing, the minority carrier injection from the gate to the channel will become small. Also, this composite channel structure can be effectively applied to recessed gate device and split gate device as well.

摘要翻译： 在具有一个导电类型和低杂质浓度的半导体区域和形成在该半导体区域中具有相反导电类型和高杂质浓度的栅区的静电感应型半导体器件中，由此限定这些栅区之间的沟道区， 在每个栅极区域周围提供具有一种导电类型和相对高的杂质浓度的辅助半导体区域，以在半导体区域中留下有效沟道区域，或者在漏极侧的整个沟道区域中与有效沟道区域相邻。 通过构造该器件，即使当沟道区域完全耗尽时，该有效沟道区域也具有相对较低的电位差，并且提供相对较宽的电流路径。 辅助半导体区域在栅极区域附近建立相对高的电位差，使得栅极区域之间的距离可以被大大地减小。 在辅助半导体区域设置在栅极区域周围的情况下，接合处的内置电位变大，使得即使在向前偏置时，从栅极到沟道的少数载流子注入也将变小。 此外，该复合沟道结构也可以有效地应用于凹陷栅极器件和分离栅极器件。

公开(公告)号：US4326209A

公开(公告)日：1982-04-20

申请号：US86670

申请日：1979-10-19

申请人： Jun-ichi Nishizawa ,  Takashi Yoshida

发明人： Jun-ichi Nishizawa ,  Takashi Yoshida

IPC分类号： H01L29/772 ,  H01L29/80

CPC分类号： H01L29/7722

摘要： A static induction transistor of the type wherein carriers are injected from a source to a drain across a potential barrier induced in a current channel and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate and to a drain bias voltage applied to the drain to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R.sub.c and the true transconductance G.sub.m of the transistor is maintained less than one and the product of the true transconductance and the series resistance R.sub.s of the transistor is maintained greater than or equal to one in the low drain current region in the operative state of the transistor. The series resistance R.sub.s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region. In an upside-down structure, the above-mentioned conditions can be easily attained by selecting respective impurity concentrations and thicknesses of a substrate and an epitaxial layer grown thereon.

摘要翻译： 一种静电感应晶体管，其中载流子从源极流到跨越在电流通道中感应的势垒的漏极，并且其中势垒的高度可以响应于施加到栅极的栅极偏置电压而变化，并且 施加到漏极的漏极偏置电压，从而控制晶体管的漏极电流的大小。 晶体管的沟道电阻Rc和真正跨导Gm的乘积保持小于1，并且晶体管的真正跨导和串联电阻Rs的乘积在低漏极电流区域中保持为大于或等于1的乘积 晶体管的工作状态。 串联电阻Rs是源极的电阻，源极到电流通道的电阻以及从当前通道的入口到位势的最大值（极值点）位置的通道电阻之和 当前渠道。 该静态感应晶体管的优点是电流 - 电压特性曲线在包括低漏极电流区域的非常宽的漏极电流范围内几乎是线性的。 在上下颠倒的结构中，通过选择基板和其上生长的外延层的各自的杂质浓度和厚度，可以容易地获得上述条件。

公开(公告)号：US4297718A

公开(公告)日：1981-10-27

申请号：US693894

申请日：1976-06-08

申请人： Jun-Ichi Nishizawa ,  Takashi Kitsuregawa

发明人： Jun-Ichi Nishizawa ,  Takashi Kitsuregawa

IPC分类号： H01L29/80 ,  H01L21/00 ,  H01L23/64 ,  H01L29/00 ,  H01L29/808

CPC分类号： H01L29/8083 ,  H01L21/00 ,  H01L23/645 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Vertical type field effect transistors are disclosed including one of the highly doped source, gate and drain regions disposed on one of the main opposite faces of one of the semiconductor substrate and the remaining region or regions disposed on the other mainface of the substrate. At least one of the regions is divided into a plurality of elongated slender portions and metallic electrodes are disposed in ohmic contact with the respective regions so as to be identical in configuration to the latter. The highly doped regions themselves may form electrodes.

摘要翻译： 公开了垂直型场效应晶体管，其包括设置在半导体衬底中的一个的主相对面之间的高掺杂源极，栅极和漏极区域以及设置在衬底的另一个主表面上的剩余区域或区域中的一个。 至少一个区域被分成多个细长的细长部分，并且金属电极与各个区域欧姆接触地设置成与后者相同。 高掺杂区域本身可以形成电极。

公开(公告)号：US4296425A

公开(公告)日：1981-10-20

申请号：US76675

申请日：1979-09-18

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： H01L21/208 ,  H01L33/28 ,  H01L33/30 ,  H01L33/38 ,  H01L33/00 ,  H01L29/203 ,  H01L29/205

CPC分类号： H01L21/02392 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L33/00

摘要： A luminescent diode comprises a p.sup.+ type substrate, at least one electron-hole recombination unit consisting of a p-type layer of a certain band gap and an n-type layer of a wider band gap epitaxially grown on said p-type layer to form a hetero junction at the interface therebetween, and a low resistivity contact disposed on an outermost surface of said unit opposite to said substrate. In the unit, said p-type layer is positioned closer to said substrate than said n-type layer. Light emitted in the vicinity of the hetero junction in the p-type layer of the unit is transmitted through this hetero junction and the n-type layer to emit from the outermost surface of the unit.

摘要翻译： 发光二极管包括p +型衬底，至少一个电子 - 空穴复合单元，由一定带隙的p型层和在所述p型层上外延生长的较宽带隙的n型层组成， 在它们之间的界面处形成异质结，并且设置在与所述基板相对的所述单元的最外表面上的低电阻率接触。 在该单元中，所述p型层位于比所述n型层更靠近所述衬底的位置。 在单元的p型层中的异质结附近发射的光通过该异质结透射，并且n型层从单元的最外表面发射。

公开(公告)号：US4199771A

公开(公告)日：1980-04-22

申请号：US893537

申请日：1978-04-04

申请人： Jun-Ichi Nishizawa ,  Takashi Yoshida

发明人： Jun-Ichi Nishizawa ,  Takashi Yoshida

IPC分类号： H01L29/80 ,  H01L21/331 ,  H01L29/73 ,  H01L29/772 ,  H01L29/74

CPC分类号： H01L29/7722

摘要： In a static induction transistor of the type wherein carriers are injected from a source region to a drain region across a potential barrier induced in a current channel, and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R.sub.c and the true transconductance (G.sub.m) of the transistor is maintained less than one and the product of the true transconductance and the series resistance R.sub.s of the transistor is maintained greater than or equal to one in the main operative state of the transistor. The series resistance R.sub.s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region.

摘要翻译： 在这种类型的静态感应晶体管中，其中载流子从源区域注入跨越在电流通道中感应的势垒的漏极区，并且其中势垒的高度可以响应于施加到 栅极，从而控制晶体管的漏极电流的大小。 晶体管的沟道电阻Rc和真正跨导（Gm）的乘积保持小于1，并且晶体管的真正跨导和串联电阻Rs的乘积在主要工作状态下保持为大于或等于1 的晶体管。 串联电阻Rs是源极的电阻，源极到电流通道的电阻以及从当前通道的入口到位势的最大值（极值点）位置的通道电阻之和 当前渠道。 该静态感应晶体管的优点是电流 - 电压特性曲线在包括低漏极电流区域的非常宽的漏极电流范围内几乎是线性的。

公开(公告)号：USRE29971E

公开(公告)日：1979-04-17

申请号：US576541

申请日：1975-05-12

申请人： Jun-ichi Nishizawa ,  Takeshi Terasaki

发明人： Jun-ichi Nishizawa ,  Takeshi Terasaki

IPC分类号： H01L29/772 ,  H03F1/32

CPC分类号： H01L29/7722 ,  H03F1/327

摘要： A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain .[.volage.]. .Iadd.voltage .Iaddend.is above the threshold voltage exhibiting a .Iadd.substantially .Iaddend.linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.