公开(公告)号：US09930786B2

公开(公告)日：2018-03-27

申请号：US15515357

申请日：2015-10-15

Applicant: Atotech Deutschland GmbH

Inventor： Andreas Skupin ,  Stefan Grüβner

IPC: C23F1/00 ,  H05K3/00 ,  B81C1/00

CPC classification number: H05K3/0055 ,  B81C1/00539 ,  H05K3/00 ,  H05K3/0088 ,  H05K2203/0796 ,  H05K2203/1545

Abstract: A desmear module for a horizontal galvanic or wet-chemical process line for metal, in particular copper, deposition on a substrate to be treated for a removal of precipitates comprising a desmear container connectable to a desmear unit, a pump and at least a first liquid connection element for connecting said pump with the desmear unit, wherein said pump is in conjunction with said desmear unit by said at least first liquid connection element; and wherein a treatment liquid level is provided inside the desmear module, which is above an intake area of the pump; wherein the desmear module further comprises at least a first liquid area, at least an adjacent second liquid area comprising the intake area of the pump, and at least a first separating element arranged between said at least first liquid area and said at least second liquid area.

公开(公告)号：US09929097B2

公开(公告)日：2018-03-27

申请号：US14719764

申请日：2015-05-22

Applicant: Ravi Nalla ,  Omar Bchir ,  Houssam Jomaa

Inventor： Ravi Nalla ,  Omar Bchir ,  Houssam Jomaa

IPC: H01L23/532 ,  C08J5/18 ,  H05K3/38 ,  H05K3/46 ,  H01L23/00 ,  H05K1/02 ,  H05K3/18

CPC classification number: H01L23/53238 ,  C08J5/18 ,  C08J2363/00 ,  H01L24/26 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0298 ,  H05K3/181 ,  H05K3/381 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2203/0773 ,  H05K2203/0796 ,  Y10T156/1052 ,  Y10T428/249921 ,  Y10T428/254 ,  Y10T428/268 ,  H01L2924/00

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170362682A1

公开(公告)日：2017-12-21

申请号：US15539570

申请日：2015-12-18

Applicant: BRGM ,  Centre National de la Recherche Scientifique (CNRS) ,  Universite d'Orleans

Inventor： Nour-Eddine Menad ,  Sylvain Guignot ,  Iskender Gokalp ,  Stéphane Bostyn ,  Yann Graz ,  Jacques Poirier

IPC: C22B15/00 ,  H05K3/22 ,  B09B3/00

CPC classification number: C22B15/0056 ,  A62D3/20 ,  B09B3/00 ,  B09B3/0016 ,  B09B3/0083 ,  B09B5/00 ,  H05K3/22 ,  H05K2203/0228 ,  H05K2203/0796 ,  H05K2203/104 ,  H05K2203/1105 ,  H05K2203/178 ,  Y02P70/613 ,  Y02W30/82 ,  Y02W30/822

Abstract: The method for separation of metals from electronic cards includes a step of processing the electronic cards in an aqueous medium under supercritical conditions. The method also a later step of crushing solid materials coming from the treatment under supercritical conditions.

公开(公告)号：US20150083602A1

公开(公告)日：2015-03-26

申请号：US14373961

申请日：2013-02-06

Applicant: Atotech Deutschland GmbH

Inventor： Richard Nichols ,  Don Jang ,  Harald Riebel ,  Frank Brüning

IPC: H05K3/38 ,  H05K3/06 ,  C25D7/06 ,  C23C18/40

CPC classification number: H05K3/387 ,  C23C18/1653 ,  C23C18/2006 ,  C23C18/2066 ,  C23C18/30 ,  C23C18/40 ,  C23C18/405 ,  C25D3/38 ,  C25D5/022 ,  C25D5/56 ,  C25D7/00 ,  C25D7/06 ,  H05K3/06 ,  H05K3/108 ,  H05K3/381 ,  H05K3/388 ,  H05K3/389 ,  H05K3/421 ,  H05K3/4644 ,  H05K2203/0789 ,  H05K2203/0793 ,  H05K2203/0796

Abstract: The present invention relates to a method for manufacture of fine line circuitry in the manufacture of printed circuit boards, IC substrates and the like. The method utilizes a first conductive layer on the smooth surface of a build-up layer and a second conductive layer selected from electrically conductive polymers, colloidal noble metals and electrically conductive carbon particles on the roughened walls of at least one opening which are formed after depositing the first conductive layer.

Abstract translation: 本发明涉及制造印刷电路板，IC基板等中的细线电路的制造方法。 该方法利用堆积层的光滑表面上的第一导电层和选自导电聚合物，胶体贵金属和在沉积后形成的至少一个开口的粗糙化壁上的导电碳颗粒的第二导电层 第一导电层。

公开(公告)号：US20150034369A1

公开(公告)日：2015-02-05

申请号：US14130741

申请日：2012-07-03

Applicant: Naoki Kashima ,  Keiichi Hasebe ,  Seiji Shika ,  Yoshinori Mabuchi ,  Yoshihiro Kato

Inventor： Naoki Kashima ,  Keiichi Hasebe ,  Seiji Shika ,  Yoshinori Mabuchi ,  Yoshihiro Kato

IPC: H05K1/03 ,  H05K1/02 ,  H05K3/07 ,  H05K3/02 ,  H05K3/18 ,  H05K3/10

CPC classification number: H05K1/0373 ,  C08G59/40 ,  C08G59/4014 ,  C08G73/0655 ,  C08J5/24 ,  C08J2379/04 ,  C08J2463/00 ,  C08K3/013 ,  C08K3/22 ,  C08K3/36 ,  C08K5/29 ,  C08K5/3415 ,  C08L63/00 ,  C08L79/04 ,  C08L79/085 ,  H05K1/0296 ,  H05K1/0366 ,  H05K3/0055 ,  H05K3/022 ,  H05K3/07 ,  H05K3/108 ,  H05K3/182 ,  H05K3/188 ,  H05K3/381 ,  H05K3/4676 ,  H05K2203/0773 ,  H05K2203/0793 ,  H05K2203/0796 ,  H05K2203/1152 ,  Y10T428/24355 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/31529

Abstract: Provided is a resin composition which enables the formation of a roughened surface having a low roughness degree on the surface of an insulation layer in a printed wiring board material when used on the insulation layer regardless of the roughening conditions employed and also enables the formation of a conductive layer having excellent adhesion properties, heat resistance, heat resistance under absorption of moisture, thermal expansion properties and chemical resistance on the roughened surface. A resin composition comprising (A) an inorganic filler that is soluble in an acid, (B) a cyanic acid ester compound and (C) an epoxy resin.

Abstract translation: 提供一种树脂组合物，其可以在绝缘层上使用时在印刷线路板材料的绝缘层的表面上形成具有低粗糙度的粗糙化表面，而不管所用的粗糙度条件如何，并且还可以形成 导电层具有优异的粘附性，耐热性，吸湿下的耐热性，在粗糙化表面上的热膨胀特性和耐化学性。 一种树脂组合物，其包含（A）可溶于酸的无机填料，（B）氰酸酯化合物和（C）环氧树脂。

公开(公告)号：US20130319749A1

公开(公告)日：2013-12-05

申请号：US13960930

申请日：2013-08-07

Applicant: Ajinomoto Co., Inc.

Inventor： Seiichiro OHASHI ,  Eiichi Hayashi ,  Shigeo Nakamura ,  Takaaki Yazawa ,  Junichi Nakamura

IPC: H05K3/42 ,  H05K1/02

CPC classification number: H05K3/02 ,  H05K1/02 ,  H05K1/0366 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/42 ,  H05K2203/0796 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 μm or below.

公开(公告)号：US08581105B2

公开(公告)日：2013-11-12

申请号：US13632742

申请日：2012-10-01

Applicant: Brian J. McDermott ,  Daniel McGowan ,  Ralph Leo Spotts, Jr. ,  Sid Tryzbiak

Inventor： Brian J. McDermott ,  Daniel McGowan ,  Ralph Leo Spotts, Jr. ,  Sid Tryzbiak

IPC: H05K1/03

CPC classification number: H05K1/032 ,  H05K1/0296 ,  H05K3/0017 ,  H05K3/0023 ,  H05K3/0055 ,  H05K3/10 ,  H05K3/381 ,  H05K3/4661 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/12361 ,  Y10T428/24331

Abstract: A process of making an article of manufacture, the process including constructing an electrical device which implements circuitry having a portion in cavities, the portion defined by an epoxy dielectric material delivered with solid content sufficient that etching the epoxy forms cavities located in, and underneath an initial surface of, the dielectric material, sufficient that the etching of the epoxy uses non-homogeneity with the solid content in bringing about formation of the cavities and sufficient that the etching of the epoxy is such that a plurality of the cavities have a cross-sectional width that is greater than a maximum depth with respect to the initial surface, wherein the etching forms the cavities, and a conductive material, a portion of the conductive material in the cavities thereby forming teeth in the cavities, such that the conductive material forms the portion of the circuitry of the electrical device.

Abstract translation: 一种制造制品的方法，该方法包括构造电气装置，该电气装置实现具有空腔中的一部分的电路，该部分由环氧介质材料限定，该固体含量足以使环氧树脂形成位于其中并位于 电介质材料的初始表面足以使环氧树脂的蚀刻在形成空腔时与固体含量不均匀，并且足以使环氧树脂的蚀刻使得多个空腔具有横截面， 相对于初始表面大于最大深度的截面宽度，其中蚀刻形成空腔，并且导电材料，空腔中的导电材料的一部分从而在空腔中形成齿，使得导电材料形成 电气设备的电路部分。

公开(公告)号：US20120067633A1

公开(公告)日：2012-03-22

申请号：US13307213

申请日：2011-11-30

Applicant: Yogo KAWASAKI ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo KAWASAKI ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/02

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.

Abstract translation: 一种多层印刷电路板，包括芯基板，分别形成在芯基板的表面上的下层层间树脂绝缘层，形成在穿透芯基板的穿透孔中的通孔导体和下层间树脂绝缘层，导体 形成在下层树脂绝缘层上的电路分别形成在导体电路和下层间树脂绝缘层上的上层间树脂绝缘层和分别形成在上层间树脂绝缘层中并位于通孔上的通孔导体 导体。

公开(公告)号：US07838779B2

公开(公告)日：2010-11-23

申请号：US11452933

申请日：2006-06-15

Applicant: Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

Inventor： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/0055 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/09863 ,  H05K2203/0796 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.

Abstract translation: 在由板状绝缘膜的一面形成的凹部形成有由布线体和蚀刻阻挡层构成的下层布线的布线基板，在基板绝缘膜的另一面形成有上层布线， 绝缘膜，上层布线和下层布线的布线体通过形成在基板绝缘膜上的通孔相互连接。 通孔为桶形，钟形或波纹管状。

公开(公告)号：US07815785B2

公开(公告)日：2010-10-19

申请号：US11756048

申请日：2007-05-31

Applicant: Walter Kronenberg ,  Jürgen Hupe

Inventor： Walter Kronenberg ,  Jürgen Hupe

IPC: C25D5/34 ,  C25D5/54 ,  C25D5/56

CPC classification number: C25D5/56 ,  H05K1/0346 ,  H05K3/188 ,  H05K2201/0154 ,  H05K2201/0329 ,  H05K2203/0796

Abstract: The present invention relates to an improved method for the direct metallization of non-conductive substrate surfaces, in particular polyimide surfaces, that is characterized by the process steps of etching the substrate surface with an acidic etching solution that contains peroxide; contacting the etched substrate surface with an acidic treatment solution that contains permanganate; activating the treated substrate surface in an acidic activation solution that contains peroxide; contacting the activated substrate surface with an acidic catalytic solution that contains at least a thiophene derivate and at least a sulfonic acid derivate; metallization of the thus treated substrate surface in an acidic galvanic metallization bath.

Abstract translation: 本发明涉及用于直接金属化非导电衬底表面，特别是聚酰亚胺表面的改进方法，其特征在于用含有过氧化物的酸性蚀刻溶液蚀刻衬底表面的工艺步骤; 使蚀刻的基底表面与含有高锰酸盐的酸性处理溶液接触; 在含有过氧化物的酸性活化溶液中活化经处理的底物表面; 使活化的底物表面与至少含有噻吩衍生物和至少一种磺酸衍生物的酸性催化溶液接触; 这样处理的基底表面在酸性电镀金属浴中的金属化。