公开(公告)号：US09106238B1

公开(公告)日：2015-08-11

申请号：US13844331

申请日：2013-03-15

Applicant: Kandou Labs, SA

Inventor： Harm Cronie ,  Brian Holden

IPC: H03M1/36 ,  H03M7/00 ,  H03M1/18

CPC classification number: H03M7/00 ,  G06F11/1072 ,  G06F12/0207 ,  H03M1/18 ,  Y02D10/13

Abstract: A sorting decoder captures the rank-order of a set of input analog signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analog-to-digital signal converters. The analog signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

Abstract translation: 排序解码器使用诸如自定时第一状态元素之类的简单逻辑组件来捕获数字域中的一组输入模拟信号的秩次，而不需要常规的模数转换器。 模拟信号各自与单调动态参考进行比较，并且所得到的比较是对于每个输入信号的自定时第一状态元素或输入信号的排序集合的最后一个成员在到达参考时的快照 信号，使得针对每个输入信号产生表示相对于其它信号值排列的信号值的不同快照。 所得到的秩序估计快照是二进制信号，然后可以通过基于基本逻辑分量的简单分类逻辑电路进一步处理二进制信号。

公开(公告)号：US09094029B2

公开(公告)日：2015-07-28

申请号：US14263753

申请日：2014-04-28

Applicant: Marvell World Trade Ltd.

Inventor： Mingguang Xu ,  Yakun Sun ,  Hui-Ling Lou

IPC: H03M7/00 ,  H03M13/00 ,  H04B7/04 ,  H04L1/00 ,  H03M13/09 ,  H03M13/11 ,  H03M13/23 ,  H03M13/29

CPC classification number: H03M7/00 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/6331 ,  H04B7/04 ,  H04B7/0456 ,  H04L1/0048

Abstract: Systems and methods are provided for determining a decoding order in a successive interference cancellation receiver. The method includes receiving, using control circuitry, a plurality of codewords. The method further includes computing at least one ordering metric for at least one of the plurality of codewords based on posterior information associated with the plurality of codewords, and determining the decoding order based on the at least one ordering metric.

Abstract translation: 提供了用于确定连续干扰消除接收机中的解码顺序的系统和方法。 该方法包括使用控制电路接收多个码字。 所述方法还包括基于与所述多个码字相关联的后验信息来计算所述多个码字中的至少一个的至少一个排序度量，以及基于所述至少一个排序度量确定所述解码顺序。

公开(公告)号：US09058436B1

公开(公告)日：2015-06-16

申请号：US13682730

申请日：2012-11-20

Applicant: ALTERA Corporation

Inventor： Gordon Chiu ,  Navid Azizi

IPC: H03M7/00 ,  G06F11/30 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4009 ,  G06F11/3072 ,  G06F13/38 ,  G06F13/385 ,  G06F13/42 ,  H03M7/00

Abstract: Methods, systems and circuits for reducing aging of at least one component of a data path are disclosed. First data transmitted over a data path may be monitored in an active state to allow generation of second data, where the second data may be transmitted in an inactive state over the data path to improve the balance of any imbalance in the static probability of one logical state versus another caused by transmission of the first data. Portions of data to be transmitted over a data path may be compared to previously-transmitted portions of data to determine a respective data bus inversion (DBI) setting each portion of data, where the DBI settings may be used to increase the toggling of bits of the data path and improve the balance of the static probability of one logical state versus another.

Abstract translation: 公开了用于减少数据路径的至少一个部件的老化的方法，系统和电路。 可以在活动状态下监视通过数据路径发送的第一数据，以允许生成第二数据，其中可以通过数据路径以非活动状态发送第二数据，以改善一个逻辑的静态概率的任何不平衡的平衡 状态与另一种由第一数据的传输引起的。 可以将通过数据路径传输的数据的部分与先前发送的数据部分进行比较，以确定设置数据的每个部分的相应数据总线反相（DBI），其中DBI设置可以用于增加数据的位的翻转 数据路径，并提高一个逻辑状态与另一个逻辑状态的静态概率的平衡。

公开(公告)号：US20150160922A1

公开(公告)日：2015-06-11

申请号：US14622860

申请日：2015-02-14

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G06F7/487 ,  G06F5/01

CPC classification number: G06F7/4876 ,  G06F5/012 ,  H03M7/00 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/158 ,  H03M13/19 ,  H03M13/23 ,  H04L9/06

Abstract: Methods and apparatus reducing the number of multipliers in Galois Field arithmetic are disclosed. Methods and apparatus for implementing n-valued Linear Feedback Shift Register (LFSR) based applications with a reduced number of multipliers are also disclosed. N-valued LFSRs with reduced numbers of multipliers in Fibonacci and in Galois configuration are demonstrated. Multiplier reduction methods are extended to n-valued functions with more than 2 inputs. Methods to create multiplier reduced multi-input n-valued function truth tables are disclosed. Methods and apparatus to implement these truth tables with a limited number of n-valued inverters are also disclosed. Scrambler/descrambler combinations with adders and multipliers over GF(2p) are provided. Communication, data storage and digital rights management systems using multiplier reduction methods and apparatus or the disclosed scrambler/descrambler combination are also provided.

Abstract translation: 公开了减少伽罗瓦域算术中的乘数的方法和装置。 还公开了用于实现具有减少数量的乘法器的基于n值线性反馈移位寄存器（LFSR）的应用的方法和装置。 证明了斐波纳契和伽罗瓦配置中乘数乘数减少的N值LFSR。 乘数减少方法扩展到具有多于2个输入的n值函数。 公开了创建乘法器减少的多输入n值函数真值表的方法。 还公开了用有限数量的n值逆变器来实现这些真值表的方法和装置。 提供了与GF（2p）上的加法器和乘法器的加扰/解扰器组合。 还提供了使用减法方法和装置或所公开的扰码器/解扰器组合的通信，数据存储和数字版权管理系统。

公开(公告)号：US20150120787A1

公开(公告)日：2015-04-30

申请号：US14590679

申请日：2015-01-06

Applicant: Yiftach Shoolman ,  Ofer Bengal

Inventor： Yiftach Shoolman ,  Ofer Bengal

IPC: G06F17/30

CPC classification number: G06F16/21 ,  G06F16/278 ,  H03M7/00 ,  H03M7/3088 ,  H03M7/707

Abstract: In some embodiments, systems for managing an in-memory NoSQL database are provided, the systems comprising a hardware processor that is configured to: receive a dataset; split the dataset into a plurality of parts of the dataset; and storing each of the plurality of parts of the dataset in a separate one of a plurality of 32-bit software architecture in-memory NoSQL databases.

Abstract translation: 在一些实施例中，提供了用于管理内存中NoSQL数据库的系统，所述系统包括被配置为：接收数据集的硬件处理器; 将数据集拆分成数据集的多个部分; 并将所述数据集的所述多个部分中的每一个存储在多个32位软件体系结构的内存NoSQL数据库中的单独的一个中。

公开(公告)号：US20150116136A1

公开(公告)日：2015-04-30

申请号：US14591665

申请日：2015-01-07

Applicant: International Characters, Inc.

Inventor： Robert D. Cameron

IPC: G06F17/20 ,  H03M7/00

CPC classification number: G06F17/20 ,  G06F17/277 ,  G06F17/30923 ,  H03M7/00

Abstract: One embodiment of the present invention is a method for increasing the speed of a computer in identifying occurrences of strings in a character stream that match a string pattern involving repetitions of characters of a particular character class. The method uses a parallel bit stream processing module of the computer, which processing module includes a processor equipped with parallel processing instructions, to form a plurality of parallel property bit streams Pj.

Abstract translation: 本发明的一个实施例是一种用于增加计算机在识别与包括特定字符类的字符的重复的字符串模式匹配的字符流中的字符串的出现的速度的方法。 该方法使用计算机的并行比特流处理模块，该处理模块包括配备有并行处理指令的处理器，以形成多个并行属性比特流Pj。

公开(公告)号：US20150016343A1

公开(公告)日：2015-01-15

申请号：US14500770

申请日：2014-09-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Rongdao YU

IPC: H04W72/04 ,  H03M7/00

CPC classification number: H04W72/0413 ,  H03M7/00 ,  H04B7/0848 ,  H04L1/00

Abstract: Disclosed are a method and a system for transmitting a data stream, aiming at increasing system capacity. The method includes: transmitting, by a first sending end, a coded first data stream to a first receiving end, and transmitting, by a second sending end, a coded second data stream to a second receiving end on time-frequency resources occupied by transmission of the first data stream by the first sending end; decoding, by the first receiving end, a first received signal received to obtain a first decoded result, and transmitting at least one decoded result in the first decoded result to the second receiving end; and decoding, by the second receiving end, a second received signal received, by using the at least one decoded result in the first decoded result to obtain a second decoded result.

Abstract translation: 公开了一种用于传输数据流的方法和系统，旨在提高系统容量。 该方法包括：通过第一发送端将编码的第一数据流发送到第一接收端，并且通过第二发送端将经编码的第二数据流发送到在传输占用的时间 - 频率资源上的第二接收端 的第一数据流由第一发送端; 通过第一接收端解码接收的第一接收信号以获得第一解码结果，并将第一解码结果中的至少一个解码结果发送到第二接收端; 以及通过使用所述第一解码结果中的所述至少一个解码结果来解码由所述第二接收端接收到的第二接收信号，以获得第二解码结果。

公开(公告)号：US08933826B2

公开(公告)日：2015-01-13

申请号：US14254102

申请日：2014-04-16

Applicant: Gurulogic Microsystems Oy

Inventor： Ossi Kalevo

IPC: H03M5/00 ,  H03M7/30 ,  H03M7/00 ,  G11B20/14 ,  H03M7/40 ,  G06K9/38 ,  G06F7/24 ,  G06T1/20

CPC classification number: H03M7/30 ,  G06F7/24 ,  G06K9/38 ,  G06T1/20 ,  G11B20/1419 ,  H03M7/00 ,  H03M7/14 ,  H03M7/4006

Abstract: An encoder encodes data to generate corresponding encoded data. The encoder includes a data processing arrangement for applying one or more encoding processes to the data to generate the encoded data. The data processing arrangement is operable to represent the data at least partially in a set of numerical value symbols, if the data is not already expressed in numerical value symbols. The data processing arrangement is operable to generate intermediate data in which the numerical value symbols are represented by original values and at least one symbol by a modified value with one or more continuum symbols generated by a continuum operator. The one or more continuum symbols modify preceding symbol values to accommodate an extended range of symbols.

Abstract translation: 编码器对数据进行编码以产生相应的编码数据。 编码器包括用于对数据应用一个或多个编码处理以产生编码数据的数据处理装置。 数据处理装置可操作以至少部分地以一组数值符号表示数据，如果数据尚未以数值符号表示。 数据处理装置可操作以产生中间数据，其中数值符号由原始值表示，至少一个符号由具有一个或多个由连续统一运算符产生的连续符号的修改值表示。 一个或多个连续符号修改先前的符号值以适应扩展的符号范围。

公开(公告)号：US20140327559A1

公开(公告)日：2014-11-06

申请号：US14263753

申请日：2014-04-28

Applicant: Marvell World Trade Ltd.

Inventor： Mingguang Xu ,  Yakun Sun ,  Hui-Ling Lou

IPC: H03M7/00

CPC classification number: H03M7/00 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/6331 ,  H04B7/04 ,  H04B7/0456 ,  H04L1/0048

Abstract: Systems and methods are provided for determining a decoding order in a successive interference cancellation receiver. The method includes receiving, using control circuitry, a plurality of codewords. The method further includes computing at least one ordering metric for at least one of the plurality of codewords based on posterior information associated with the plurality of codewords, and determining the decoding order based on the at least one ordering metric.

Abstract translation: 提供了用于确定连续干扰消除接收机中的解码顺序的系统和方法。 该方法包括使用控制电路接收多个码字。 所述方法还包括基于与所述多个码字相关联的后验信息来计算所述多个码字中的至少一个的至少一个排序度量，以及基于所述至少一个排序度量确定所述解码顺序。

公开(公告)号：US08847795B2

公开(公告)日：2014-09-30

申请号：US14128718

申请日：2012-06-26

Applicant: Julien Faure ,  Pierrick Philippe

Inventor： Julien Faure ,  Pierrick Philippe

IPC: H03M7/00 ,  G10L19/02 ,  H04L27/26 ,  H03M7/30 ,  G10L19/12 ,  G10L19/022 ,  H03M7/46 ,  G10L19/008

CPC classification number: H03M7/00 ,  G10L19/008 ,  G10L19/0212 ,  G10L19/022 ,  G10L19/12 ,  H03M7/30 ,  H03M7/46 ,  H04L27/26

Abstract: Coding/decoding of a digital signal, consisting of successive blocks of samples, the coding being of the transform with overlap type and comprising, upon analysis, the application of a weighting window to two blocks of M successive samples. In particular, this weighting window is asymmetric and comprises four distinct portions extending successively over the two aforesaid blocks, with: a first portion, increasing over a first interval of samples, a second portion, constant at a value of 1 over a second interval, a third portion, decreasing over a third interval, and a fourth portion, constant at a value of 0 over a fourth interval.

Abstract translation: 由连续的样本块组成的数字信号的编码/解码，编码是具有重叠类型的变换，并且在分析时包括将加权窗口应用于M个连续采样的两个块。 特别地，该加权窗口是不对称的，并且包括在两个上述块上连续延伸的四个不同部分，其中：第一部分，在第一采样间隔上增加第二部分，在第二间隔上恒定为值1， 第三部分，在第三间隔上减小，第四部分在第四个间隔内以0值恒定。