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公开(公告)号：US20190385656A1
公开(公告)日：2019-12-19
申请号：US16431158
申请日：2019-06-04
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Po-Hao Lee , Ku-Feng Lin , Yi-Chun Shih , Yu-Der Chih
Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
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公开(公告)号：US20250118367A1
公开(公告)日：2025-04-10
申请号：US18938961
申请日：2024-11-06
Inventor： Hiroki Noguchi , Yu-Der Chih , Yih Wang
Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
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公开(公告)号：US12229003B2
公开(公告)日：2025-02-18
申请号：US18230619
申请日：2023-08-04
Inventor： Hiroki Noguchi , Yu-Der Chih , Hsueh-Chih Yang , Randy Osborne , Win San Khwa
Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
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114.发明授权公开(公告)号：US12217819B2
公开(公告)日：2025-02-04
申请号：US17656425
申请日：2022-03-25
Inventor： Yu-Der Chih , Chia-Fu Lee
IPC: G11C7/10 , G11C7/12 , G11C8/08 , G11C11/4074
Abstract: A method for performing an in-memory computation includes: storing data in memory cells of a memory array, the data including weights for computation; determining whether an update command to change at least one of the weights is received; in response to receiving the update command, performing a write operation on the memory array to update the at least one weight; and disabling the write operation on the memory array until receiving a next update command to change the at least one weight.
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公开(公告)号：US12164882B2
公开(公告)日：2024-12-10
申请号：US17203130
申请日：2021-03-16
Inventor： Yu-Der Chih , Hidehiro Fujiwara , Yi-Chun Shih , Po-Hao Lee , Yen-Huei Chen , Chia-Fu Lee , Jonathan Tsung-Yung Chang
IPC: G06F7/501 , G06F7/53 , G11C7/10 , G11C11/4074
Abstract: A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.
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Patent Agency Ranking
公开(公告)号：US20240385802A1
公开(公告)日：2024-11-21
申请号：US18469879
申请日：2023-09-19
Inventor： Yu-Der Chih , Chia-Fu Lee , Jonathan Tsung-Yung Chang
Abstract: A computing-in-memory circuit includes an input circuit to receive a number (N) of input pairs, each of the N input pairs comprising a first one and a second one of N exponents, and a first one and a second one of N mantissas; a first adder circuit to generate N exponent sums based on the first and second exponents of the N input pairs; a subtractor circuit configured to calculate N exponent differences, each of the N exponent differences being equal to a difference between a corresponding one of the N exponent sums and a largest one of the N exponent sums; and a comparator circuit to compare each of the N exponent differences with a threshold to generate N control signals. N mantissa products of the first and second mantissas of the N input pairs, respectively, are to be selectively combined based on the N control signals.
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公开(公告)号：US20240355389A1
公开(公告)日：2024-10-24
申请号：US18760971
申请日：2024-07-01
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0033 , G11C2213/79
Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.
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公开(公告)号：US20240170031A1
公开(公告)日：2024-05-23
申请号：US18424164
申请日：2024-01-26
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
CPC classification number: G11C7/08 , G11C7/067 , G11C7/1039 , G11C11/1673 , G11C29/42
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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公开(公告)号：US20240153558A1
公开(公告)日：2024-05-09
申请号：US18411758
申请日：2024-01-12
Inventor： Yu-Der Chih , Chung-Cheng Chou , Chun-Yun Wu , Chen-Ming Hung
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0064
Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
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公开(公告)号：US11973502B2
公开(公告)日：2024-04-30
申请号：US18310143
申请日：2023-05-01
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: H03K3/356
CPC classification number: H03K3/35613
Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
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