公开(公告)号：US20170033429A1

公开(公告)日：2017-02-02

申请号：US15149841

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Chengjie Zuo ,  Je-Hsiung Jeffrey Lan ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01P7/06 ,  H01P7/10

CPC classification number: H01P7/06 ,  H01P7/10

Abstract: An apparatus includes a tunable cavity resonator that includes conductive walls that form a tunable cavity. The tunable cavity has first dimensions when one or more phase change material layers within the tunable cavity have a first state. The tunable cavity has second dimensions when the one or more phase change material layers have a second state.

Abstract translation: 一种装置包括可调谐腔谐振器，其包括形成可调谐空腔的导电壁。 当可调谐空腔内的一个或多个相变材料层具有第一状态时，可调谐空腔具有第一尺寸。 当一个或多个相变材料层具有第二状态时，可调谐腔具有第二维度。

公开(公告)号：US09560745B2

公开(公告)日：2017-01-31

申请号：US14498230

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  David Francis Berdy

IPC: H01L21/768 ,  H05K1/02 ,  C23F1/02 ,  H05K1/03 ,  H05K1/09 ,  H01L23/00

CPC classification number: H05K1/0271 ,  C23F1/02 ,  H01L21/768 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0154 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.

Abstract translation: 器件包括在衬底（例如，半导体管芯或其他集成电路）的至少两个应力结构域之间的应力消除区域。 应力消除区域包括导电结构，电耦合应力区域的电路，导电结构设置在该应力区域之间。

公开(公告)号：US09548350B2

公开(公告)日：2017-01-17

申请号：US14177072

申请日：2014-02-10

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Donald William Kidwell, Jr. ,  Jon Bradley Lasiter ,  Kwan-Yu Lai ,  Jitae Kim ,  Ravindra Vaman Shenoy

IPC: H01L29/00 ,  H01L49/02 ,  H01L27/08 ,  H01L23/48 ,  H01G4/33 ,  H01G4/012 ,  H01L21/48 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract translation: 提供的空间效率电容器具有比传统设计更高的品质因数，并且改善了从直通玻璃通孔（TGV）到电介质的电能的耦合。 例如，提供了具有非矩形横截面的TGV，其中TGV的一端耦合到第一金属板。 在第一金属板上形成电介质材料。 第二金属板以与第一金属板的至少一部分重叠以形成电介质材料的至少一个重叠区域的方式形成在电介质材料上。 重叠区域的周边的至少一部分是非平面的。 重叠区域可以形成为环形的多个部分中的大致四分之一环形的闭环形状和/或大致一半的环形形状。

公开(公告)号：US09478348B2

公开(公告)日：2016-10-25

申请号：US14313241

申请日：2014-06-24

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  David Francis Berdy ,  Jonghae Kim

IPC: H01F5/00 ,  H01F27/29 ,  H01F7/06 ,  H01F27/28 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L49/02 ,  H01L23/15

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/04 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/15 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  Y10T29/49075 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Abstract translation: 方法和装置，其中所述方法在基底中形成第一多个通孔，还包括将所述第一多个通孔形成为基本上相同的高度。 该方法在衬底外部形成多个导电迹线，并将多个导电迹线耦合到第一多个通孔：其中多个导电迹线和第一多个通孔包括多个导电匝，并且其中多个导电 匝在基本上在第一平面内的螺旋构造。

公开(公告)号：US20160248149A1

公开(公告)日：2016-08-25

申请号：US14627863

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC: H01Q1/36 ,  H01Q7/00

CPC classification number: H01Q1/36 ,  H01Q1/2283 ,  H01Q7/00 ,  H05K1/115 ,  H05K1/119 ,  H05K1/165 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2201/10098

Abstract: An apparatus includes a substrate package and a three dimensional (3D) antenna structure formed in the substrate package. The 3D antenna structure includes multiple substructures to enable the 3D antenna structure to operate as a beam-forming antenna. Each of the multiple substructures has a slanted-plate configuration or a slanted-loop configuration.

Abstract translation: 一种装置包括衬底封装和形成在衬底封装中的三维（3D）天线结构。 3D天线结构包括多个子结构，以使3D天线结构能够作为波束形成天线工作。 多个子结构中的每一个具有倾斜板配置或倾斜环配置。

公开(公告)号：US09425761B2

公开(公告)日：2016-08-23

申请号：US14055707

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

IPC: H03H7/01 ,  H04B1/04

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 贯通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

公开(公告)号：US09379802B2

公开(公告)日：2016-06-28

申请号：US14684072

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC: H04B1/06 ,  H04B1/44 ,  H03C7/02 ,  H01Q11/12 ,  H04M1/00 ,  H04B7/08 ,  H04B1/16 ,  H04B1/00 ,  H04B1/18

CPC classification number: H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

公开(公告)号：US09368564B2

公开(公告)日：2016-06-14

申请号：US14229317

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez

IPC: H01L21/48 ,  H01L49/02 ,  H01F17/00

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/002 ,  H01L21/486 ,  H01L21/4889 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract translation: 基座在支撑表面上以间距间隔开。 导电构件，可选择铜或其他金属柱，从基垫向上延伸到顶部焊盘。 顶部焊盘互连器以构造在基板之间的电感器电流路径的配置连接顶部焊盘。

公开(公告)号：US09264013B2

公开(公告)日：2016-02-16

申请号：US14019821

申请日：2013-09-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

公开(公告)号：US20150115403A1

公开(公告)日：2015-04-30

申请号：US14063934

申请日：2013-10-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。