公开(公告)号：US09671671B2

公开(公告)日：2017-06-06

申请号：US14050522

申请日：2013-10-10

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Wee Chin Judy Lim ,  David Gani ,  Hk Looi ,  Bs Aw ,  Cheng-hai Cheh

IPC: G02F1/29 ,  G02F1/35 ,  B23K1/00 ,  B23K101/38

CPC classification number: G02F1/29 ,  B23K1/0016 ,  B23K2101/38 ,  G02F2001/294 ,  G02F2202/28 ,  Y10T156/10

Abstract: An optical assembly may include a substrate, a housing carried by the substrate and having at least one adhesive-receiving recess in an upper surface thereof, and a lens carried by the housing. The optical assembly may also include a liquid crystal focus cell adjacent the lens and including cell layers and pairs of electrically conductive contacts associated therewith. The optical assembly may also include at least one electrically conductive member within the at least one adhesive-receiving recess and coupling together each pair of the electrically conductive contacts, and an adhesive body in the at least one adhesive-receiving recess covering the at least one electrically conductive member.

公开(公告)号：US20170148604A1

公开(公告)日：2017-05-25

申请号：US15150895

申请日：2016-05-10

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS PTE LTD

Inventor： Davide Giuseppe Patti ,  Myung Sung Kim

IPC: H01J19/02 ,  H01J21/20 ,  H01J21/04 ,  H01J9/18

CPC classification number: H01J19/02 ,  H01J9/025 ,  H01J9/18 ,  H01J21/04 ,  H01J21/105 ,  H01J21/20 ,  H01J2209/012 ,  H01J2209/02

Abstract: A vacuum integrated electronic device has an anode region of conductive material; an insulating region on top of the anode region; a cavity extending through the insulating region and having a sidewall; and a cathode region. The cathode region has a tip portion extending peripherally within the cavity, adjacent to the sidewall of the cavity. The cathode region is formed by tilted deposition, carried out at an angle of 30-60° with respect to a perpendicular to the surface of device.

公开(公告)号：US09598278B2

公开(公告)日：2017-03-21

申请号：US14679906

申请日：2015-04-06

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Olivier Le Neel ,  Tien Choy Loh

IPC: H01L29/84 ,  H01L27/14 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2203/0127

Abstract: The present disclosure is directed to a device that includes a substrate and a sensor formed on the substrate. The sensor includes a chamber formed from a plurality of integrated cavities, a membrane above the substrate, the membrane having a plurality of openings, each opening positioned above one of the cavities, and a plurality of diamond shaped anchors positioned between the membrane and the substrate, the anchors positioned between each of the cavities. A center of each opening is also a center of one of the cavities.

公开(公告)号：US20170053856A1

公开(公告)日：2017-02-23

申请号：US14981338

申请日：2015-12-28

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4853 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a die attachment pad; a stud bump located on the die attachment pad and in direct contact with the die attachment pad; a first die located on the stud bump and electrically coupled to the stud bump; and a conductive attachment material located between the die attachment pad and the first die.

Abstract translation: 本公开的实施例涉及半导体器件及其制造方法。 半导体器件包括：管芯附接垫; 位于模具附接垫上并与模具附接垫直接接触的柱形凸块; 位于所述柱形凸块上并电耦合到所述柱形凸块的第一模具; 以及位于管芯附接垫和第一管芯之间的导电附着材料。

公开(公告)号：US20170052040A1

公开(公告)日：2017-02-23

申请号：US14981185

申请日：2015-12-28

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: G01D5/26 ,  H05K3/32 ,  H05K3/30 ,  H05K1/18 ,  H05K3/28

CPC classification number: H05K3/32 ,  G01D11/245 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K1/181 ,  H05K3/284 ,  H05K3/303 ,  H05K2201/0108 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2203/1327 ,  H01L2924/00012

Abstract: A proximity sensor is provided according to the embodiments of the present disclosure, comprising: a sensor chip; a light-emitting device; a substrate, the sensor chip and the light-emitting device being located on the substrate; a transparent molding material covering a light-emitting surface of the light-emitting device; and a non-transparent molding material separating the transparent molding material from the sensor chip.

Abstract translation: 根据本公开的实施例提供接近传感器，包括：传感器芯片; 发光装置; 衬底，传感器芯片和发光器件位于衬底上; 覆盖发光装置的发光面的透明成型材料; 以及将透明模塑材料与传感器芯片分开的不透明模塑材料。

公开(公告)号：US09576912B1

公开(公告)日：2017-02-21

申请号：US14957865

申请日：2015-12-03

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/023 ,  H01L2924/07025

Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.

Abstract translation: 晶片级芯片级封装（WLCSP）包括半导体衬底，半导体衬底上的后端（BEOL）层，并且具有从半导体衬底的相邻外围边缘向内凹陷的外围边缘。 第一电介质层在BEOL层上方并且缠绕在BEOL层的外围边缘周围。 再分布层在第一介电层上方，第二介电层位于再分布层上。

公开(公告)号：US20160372426A1

公开(公告)日：2016-12-22

申请号：US15251209

申请日：2016-08-30

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En Luan

IPC: H01L23/00 ,  H01L23/18 ,  H01L21/78 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/18 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/3511

Abstract: A method includes forming a molded panel that includes a number of integrated circuits, fan-out components and stiffeners embedded in an encapsulation material. A redistribution layer is formed over the integrated circuits and the fan-out components. The redistribution layer is electrically coupled to contacts of the integrated circuits. The molded panel is singulated to form electronic devices. Each electronic device each an integrated circuit that is separated from a fan-out component by a portion of the encapsulation material and a stiffener separated from the fan-out component by a second portion of the encapsulation material.

Abstract translation: 一种方法包括形成包括多个集成电路，嵌入在封装材料中的扇出部件和加强件的模制板。 在集成电路和扇出组件上形成再分配层。 再分配层电耦合到集成电路的触点。 将模制板分割成电子装置。 每个电子设备各自具有通过封装材料的一部分与扇出部件分离的集成电路，以及通过封装材料的第二部分与扇出部件分离的加强件。

公开(公告)号：US09524866B2

公开(公告)日：2016-12-20

申请号：US14957141

申请日：2015-12-02

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Chong Jieh Chew

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/02252 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/033 ,  H01L21/31144

Abstract: A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

公开(公告)号：US20160293559A1

公开(公告)日：2016-10-06

申请号：US14674891

申请日：2015-03-31

Applicant: STMicroelectronics Pte Ltd

Inventor： Yun Liu ,  Jerome Teysseyre ,  Yonggang Jin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has recess at a perimeter of the semiconductor die. The semiconductor package includes an encapsulation layer that is located over the semiconductor die filling the recess and surrounding side surfaces of the pillars. The package may be formed on a wafer with a plurality of die and may be singulated into a plurality of packages.

Abstract translation: 一个或多个实施例涉及包括柱和凸块结构的半导体封装。 半导体封装包括在半导体管芯的周边具有凹部的管芯。 半导体封装包括封装层，该封装层位于半导体管芯上方，该封装层填充凹槽并且围绕柱的周围侧表面。 封装可以形成在具有多个管芯的晶片上，并且可以被单个化成多个封装。

公开(公告)号：US09455292B2

公开(公告)日：2016-09-27

申请号：US14741561

申请日：2015-06-17

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En Luan

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2224/48095 ,  H01L2224/73265

Abstract: An image sensing device may include an interconnect layer, an image sensor IC coupled to the interconnect layer and having an image sensing surface, and an IR filter aligned with the image sensing surface opposite the interconnect layer. The image sensing device may include a flexible interconnect layer aligned with the interconnect layer and having a flexible substrate extending laterally outwardly from the interconnect layer, and electrically conductive traces on the flexible substrate. The image sensing device may also include solder bodies coupling the interconnect layer and the flexible interconnect layer and also defining a gap between the interconnect layer and the flexible interconnect layer.

Abstract translation: 图像感测装置可以包括互连层，耦合到互连层并具有图像感测表面的图像传感器IC和与互连层相对的图像感测表面对准的IR滤光器。 图像感测装置可以包括与互连层对准的柔性互连层，并且具有从互连层横向向外延伸的柔性衬底以及柔性衬底上的导电迹线。 图像感测装置还可以包括耦合互连层和柔性互连层并且还限定互连层和柔性互连层之间的间隙的焊料体。