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    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
    108.
    发明授权
    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
    用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化

    公开(公告)号：US08969923B2

    公开(公告)日：2015-03-03

    申请号：US14334653

    申请日：2014-07-17

    Applicant: SanDisk 3D LLC

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L23/52 ,  G11C5/06

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

    Abstract translation: 为三维存储器的存储器层布局提供了装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于用于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。 公开其他方面。

    Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning
    109.
    发明授权
    Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning 有权
    使用双侧壁图案形成存储器线和结构的装置和方法，用于四次半间距浮雕图案化

    公开(公告)号：US08679967B2

    公开(公告)日：2014-03-25

    申请号：US12911887

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Yoichiro Tanaka

    IPC: H01L21/4763

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。

    APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING
    110.
    发明申请
    APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING 有权
    使用双重格式化方式形成记忆线和结构的四种方法的设备和方法

    公开(公告)号：US20110095434A1

    公开(公告)日：2011-04-28

    申请号：US12911887

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Yoichiro Tanaka

    IPC: H01L23/48 ,  H01L21/28

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。

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