公开(公告)号：US20180108655A1

公开(公告)日：2018-04-19

申请号：US15294906

申请日：2016-10-17

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Dechao Guo ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

公开(公告)号：US09735162B2

公开(公告)日：2017-08-15

申请号：US14874390

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L29/66 ,  H01L21/311 ,  H01L29/417 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

公开(公告)号：US20170194452A1

公开(公告)日：2017-07-06

申请号：US15207014

申请日：2016-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/76897 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/78

Abstract: A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on source-drain areas between the sacrificial gates. A contact liner and contact material are deposited. The liner and the contact material are removed from above the sacrificial gates. Contact areas are blocked with one or more masking materials and etched. The masking material is removed. The contact material is partially recessed and a nitride liner deposited. An oxide layer is deposited and the sacrificial gate is removed. A metal gate is formed on the channel region and recessed. Insulator material and metal gate material are recessed and a cap is formed over the gate.

公开(公告)号：US20160379882A1

公开(公告)日：2016-12-29

申请号：US15259220

申请日：2016-09-08

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

公开(公告)号：US20160351687A1

公开(公告)日：2016-12-01

申请号：US15235935

申请日：2016-08-12

Applicant: International Business Machines Corporation

Inventor： Gregory Costrini ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Richard S. Wise

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/51 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/517 ,  H01L29/6681

Abstract: Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.

公开(公告)号：US09431395B2

公开(公告)日：2016-08-30

申请号：US14320760

申请日：2014-07-01

Applicant: International Business Machines Corporation

Inventor： Gregory Costrini ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Richard S. Wise

IPC: H01L29/51 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/517 ,  H01L29/6681

Abstract: Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.

Abstract translation: 在形成一次性栅极结构之前，可以在半导体鳍片的表面上形成含半导体氧化物的栅极电介质。 可以形成高介电常数（高k）电介质间隔物以保护每个含半导体氧化物的栅极电介质。 高k电介质间隔物的形成可以在通过移除一次性栅极结构或者在形成一次性栅极结构之前形成栅极空腔之后进行。 高k电介质间隔物可以在垂直延伸栅极腔的各向异性蚀刻期间用作保护层，并且可以在栅腔的垂直延伸之后被去除。 可以去除含半导体氧化物的栅极电介质的子集，以形成用于第一类型器件的高k栅极电介质，而含半导体氧化物的栅极电介质的另一子集可用作第二类型器件的栅极电介质。 栅极腔的垂直延伸增加了鳍状场效应晶体管中的沟道宽度。

公开(公告)号：US20160181250A1

公开(公告)日：2016-06-23

申请号：US14581472

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Ravikumar Ramachandran ,  Reinaldo Ariel Vega

IPC: H01L27/108 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/267

CPC classification number: H01L27/10802 ,  H01L27/10844 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

Abstract translation: 本发明的实施例提供了用于制造无电容器DRAM器件的改进的方法和结构，有时称为ZRAM器件。 在由翅片通道部分和凸通道部分组成的鳍式场效应晶体管（finFET）中形成通道。 翅片通道部分可以由第一半导体材料构成，并且凸通道部分可以由第二不同的半导体材料构成。 在实施例中，金属栅极设置在沟道区的细长表面周围，但不设置在沟道区的短表面上。 第一间隔件设置成与栅极相邻并且与沟道区的短表面直接物理接触，并且第二间隔件设置成与第一间隔物相邻。

公开(公告)号：US20160035841A1

公开(公告)日：2016-02-04

申请号：US14881766

申请日：2015-10-13

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L29/40 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

公开(公告)号：US20160027893A1

公开(公告)日：2016-01-28

申请号：US14875049

申请日：2015-10-05

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Sean M. Polvino ,  Ravikumar Ramachandran ,  Shahab Siddiqui

IPC: H01L29/51 ,  H01L29/423

CPC classification number: H01L29/513 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.

公开(公告)号：US20150371948A1

公开(公告)日：2015-12-24

申请号：US14837854

申请日：2015-08-27

Applicant: International Business Machines Corporation

Inventor： Rosa A. Orozco-Teran ,  Ravikumar Ramachandran ,  John A. Fitzsimmons ,  Russell H. Arndt ,  David L. Rath

IPC: H01L23/522 ,  H01L29/49 ,  H01L29/45 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在第一金属层的顶部上形成具有第一金属层和多个电介质层的半导体结构; 通过所述多个电介质层产生一个或多个开口以暴露所述多个电介质层下面的所述第一金属层; 使所述一个或多个开口向下扩展到所述第一金属层中并且水平地扩展到所述多个介电层下面的区域中; 在所述多个电介质层内的所述一个或多个开口的衬里侧壁中施加一层衬里材料; 并用导电材料填充膨胀的一个或多个开口。